tree e515fe6a1e4504870fc11c6cc3c6fa1251f81b11
parent c90795076b30c33a95bcaf6d89979543d31fdde1
author Marek Vasut <marek.vasut+renesas@mailbox.org> 1725136307 +0200
committer Marek Vasut <marek.vasut+renesas@mailbox.org> 1725837033 +0200

mtd: spi: renesas: Configure RPC PHY timing registers

Make sure RPC PHY timing registers are configured before performing
bus access. These registers might have been left unconfigured or may
have been configured by a prior stage bootloader and leaving them
unconfigured or misconfigured would interfere with U-Boot operation.

Set PHYOFFSET1 DDRTMG field to 3 which enables DDR timing adjustment
when SPIDRE or DRDRE = 0 and set PHYOFFSET2 OCTTMG field to 4 which
makes the interface operate in Serial flash or HyperFlash mode.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>