tree 730993df736380d8b77fb4128fd6a0e3f4c0b663
parent 9ac4ffbde1a5015c9929ee8578d3811b716e2fd3
author York Sun <yorksun@freescale.com> 1370288346 -0700
committer York Sun <yorksun@freescale.com> 1385408626 -0800

powerpc/mpc8xxx: Extend DDR registers' fields

Some DDR registers' fields have expanded to accommodate larger values.
These changes are backward compatible. Some fields are removed for newer
DDR controllers. Writing to those fields are safely ignored.

TIMING_CFG_2 register is fixed. Additive latency is added to RD_TO_PRE
automatically. It was a misunderstanding in commit c360ceac.

Signed-off-by: York Sun <yorksun@freescale.com>