ddr: altera: Fix ad-hoc iterative division implementation
Contemporary CPUs can perform division just fine, use this
functionality and zap another implementation of iterative
division :-)
Signed-off-by: Marek Vasut <marex@denx.de>
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 8c56f02..28e32ff 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -2185,7 +2185,6 @@
{
uint32_t p, d, rank_bgn, sr;
uint32_t dtaps_per_ptap;
- uint32_t tmp_delay;
uint32_t bit_chk;
uint32_t grp_calibrated;
uint32_t write_group, write_test_bgn;
@@ -2200,14 +2199,8 @@
write_test_bgn = test_bgn;
/* USER Determine number of delay taps for each phase tap */
- dtaps_per_ptap = 0;
- tmp_delay = 0;
- while (tmp_delay < IO_DELAY_PER_OPA_TAP) {
- dtaps_per_ptap++;
- tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
- }
- dtaps_per_ptap--;
- tmp_delay = 0;
+ dtaps_per_ptap = DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP,
+ IO_DELAY_PER_DQS_EN_DCHAIN_TAP) - 1;
/* update info for sims */
reg_file_set_group(read_group);