diff --git a/cpu/ppc4xx/40x_spd_sdram.c b/cpu/ppc4xx/40x_spd_sdram.c
index 75bd70d..83fa709 100644
--- a/cpu/ppc4xx/40x_spd_sdram.c
+++ b/cpu/ppc4xx/40x_spd_sdram.c
@@ -422,7 +422,7 @@
 	 * program all the registers.
 	 * -------------------------------------------------------------------*/
 
-#define mtsdram0(reg, data)  mtdcr(memcfga,reg);mtdcr(memcfgd,data)
+#define mtsdram0(reg, data)  mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,data)
 	/* disable memcontroller so updates work */
 	mtsdram0( mem_mcopt1, 0 );
 
diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c
index f26fcda..c93f23a 100644
--- a/cpu/ppc4xx/44x_spd_ddr.c
+++ b/cpu/ppc4xx/44x_spd_ddr.c
@@ -192,8 +192,8 @@
 	/*
 	 * Soft-reset SDRAM controller.
 	 */
-	mtsdr(sdr_srst, SDR0_SRST_DMC);
-	mtsdr(sdr_srst, 0x00000000);
+	mtsdr(SDR0_SRST, SDR0_SRST_DMC);
+	mtsdr(SDR0_SRST, 0x00000000);
 #endif
 
 	/*
@@ -848,11 +848,11 @@
 		 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55}};
 
 	for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
-		mtdcr(memcfga, mem_b0cr + (bxcr_num << 2));
-		if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
+		mtdcr(SDRAM0_CFGADDR, mem_b0cr + (bxcr_num << 2));
+		if ((mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
 			/* Bank is enabled */
 			membase = (unsigned long*)
-				(mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK);
+				(mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBA_MASK);
 
 			/*
 			 * Run the short memory test
@@ -1086,8 +1086,8 @@
 	 * Set the BxCR regs.  First, wipe out the bank config registers.
 	 */
 	for (bx_cr_num = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
-		mtdcr(memcfga, mem_b0cr + (bx_cr_num << 2));
-		mtdcr(memcfgd, 0x00000000);
+		mtdcr(SDRAM0_CFGADDR, mem_b0cr + (bx_cr_num << 2));
+		mtdcr(SDRAM0_CFGDATA, 0x00000000);
 		bank_parms[bx_cr_num].bank_size_bytes = 0;
 	}
 
@@ -1232,12 +1232,12 @@
 	/* Set the SDRAM0_BxCR regs thanks to sort tables */
 	for (bx_cr_num = 0, bank_base_addr = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
 		if (bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes) {
-			mtdcr(memcfga, mem_b0cr + (sorted_bank_num[bx_cr_num] << 2));
-			temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK |
+			mtdcr(SDRAM0_CFGADDR, mem_b0cr + (sorted_bank_num[bx_cr_num] << 2));
+			temp = mfdcr(SDRAM0_CFGDATA) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK |
 						  SDRAM_BXCR_SDAM_MASK | SDRAM_BXCR_SDBE);
 			temp = temp | (bank_base_addr & SDRAM_BXCR_SDBA_MASK) |
 				bank_parms[sorted_bank_num[bx_cr_num]].cr;
-			mtdcr(memcfgd, temp);
+			mtdcr(SDRAM0_CFGDATA, temp);
 			bank_base_addr += bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes;
 			debug("SDRAM0_B%dCR=0x%08lx\n", sorted_bank_num[bx_cr_num], temp);
 		}
diff --git a/cpu/ppc4xx/4xx_pci.c b/cpu/ppc4xx/4xx_pci.c
index 184cef5..e97f32c 100644
--- a/cpu/ppc4xx/4xx_pci.c
+++ b/cpu/ppc4xx/4xx_pci.c
@@ -100,7 +100,7 @@
 	 * The arbiter is enabled in this place because of
 	 * compatibility reasons.
 	 */
-	mtdcr(cpc0_pci, mfdcr(cpc0_pci) | CPC0_PCI_ARBIT_EN);
+	mtdcr(CPC0_PCI, mfdcr(CPC0_PCI) | CPC0_PCI_ARBIT_EN);
 #endif /* CONFIG_405EP */
 
 	return 1;
@@ -118,10 +118,10 @@
 int __is_pci_host(struct pci_controller *hose)
 {
 #if defined(CONFIG_405GP)
-	if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
+	if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN)
 		return 1;
 #elif defined (CONFIG_405EP)
-	if (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN)
+	if (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN)
 		return 1;
 #endif
 	return 0;
@@ -491,7 +491,7 @@
 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 	unsigned long strap;
 
-	mfsdr(sdr_sdstp1,strap);
+	mfsdr(SDR0_SDSTP1,strap);
 	if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
 		printf("PCI: SDR0_STRP1[PISE] not set.\n");
 		printf("PCI: Configuration aborted.\n");
@@ -500,7 +500,7 @@
 #elif defined(CONFIG_440GP)
 	unsigned long strap;
 
-	strap = mfdcr(cpc0_strp1);
+	strap = mfdcr(CPC0_STRP1);
 	if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
 		printf("PCI: CPC0_STRP1[PISE] not set.\n");
 		printf("PCI: Configuration aborted.\n");
diff --git a/cpu/ppc4xx/4xx_uart.c b/cpu/ppc4xx/4xx_uart.c
index 0780624..8de6542 100644
--- a/cpu/ppc4xx/4xx_uart.c
+++ b/cpu/ppc4xx/4xx_uart.c
@@ -90,7 +90,7 @@
 #define CR0_EXTCLK_ENA  0x00600000
 #define CR0_UDIV_POS    16
 #define UDIV_SUBTRACT	1
-#define UART0_SDR	cntrl0
+#define UART0_SDR	CPC0_CR0
 #define MFREG(a, d)	d = mfdcr(a)
 #define MTREG(a, d)	mtdcr(a, d)
 #else /* #if defined(CONFIG_440GP) */
@@ -99,18 +99,18 @@
 #define CR0_EXTCLK_ENA  0x00800000
 #define CR0_UDIV_POS    0
 #define UDIV_SUBTRACT	0
-#define UART0_SDR	sdr_uart0
-#define UART1_SDR	sdr_uart1
+#define UART0_SDR	SDR0_UART0
+#define UART1_SDR	SDR0_UART1
 #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
     defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define UART2_SDR	sdr_uart2
+#define UART2_SDR	SDR0_UART2
 #endif
 #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
     defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define UART3_SDR	sdr_uart3
+#define UART3_SDR	SDR0_UART3
 #endif
 #define MFREG(a, d)	mfsdr(a, d)
 #define MTREG(a, d)	mtsdr(a, d)
@@ -130,8 +130,8 @@
 #define CR0_EXTCLK_ENA	0x00800000
 #define CR0_UDIV_POS	0
 #define UDIV_SUBTRACT	0
-#define UART0_SDR	sdr_uart0
-#define UART1_SDR	sdr_uart1
+#define UART0_SDR	SDR0_UART0
+#define UART1_SDR	SDR0_UART1
 #else /* CONFIG_405GP || CONFIG_405CR */
 #define UART0_BASE      0xef600300
 #define UART1_BASE      0xef600400
@@ -282,7 +282,7 @@
 	u32 reg;
 
 	/* check the pll feedback source */
-	mfcpr(cprpllc, cpr_pllc);
+	mfcpr(CPR0_PLLC, cpr_pllc);
 
 	get_sys_info(&sysinfo);
 
@@ -312,10 +312,10 @@
 	}
 
 	*pudiv = udiv;
-	mfcpr(cprperd0, reg);
+	mfcpr(CPC0_PERD0, reg);
 	reg &= ~0x0000ffff;
 	reg |= ((udiv - 0) << 8) | (udiv - 0);
-	mtcpr(cprperd0, reg);
+	mtcpr(CPC0_PERD0, reg);
 	*pbdiv = div / udiv;
 }
 #endif /* defined(CONFIG_440) && !defined(CONFIG_SYS_EXT_SERIAL_CLK) */
@@ -412,7 +412,7 @@
 	clk = tmp = reg = 0;
 #else
 #ifdef CONFIG_405EP
-	reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
+	reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK);
 	clk = gd->cpu_clk;
 	tmp = CONFIG_SYS_BASE_BAUD * 16;
 	udiv = (clk + tmp / 2) / tmp;
@@ -420,9 +420,9 @@
 		udiv = UDIV_MAX;
 	reg |= (udiv) << UCR0_UDIV_POS;	        /* set the UART divisor */
 	reg |= (udiv) << UCR1_UDIV_POS;	        /* set the UART divisor */
-	mtdcr (cpc0_ucr, reg);
+	mtdcr (CPC0_UCR, reg);
 #else /* CONFIG_405EP */
-	reg = mfdcr(cntrl0) & ~CR0_MASK;
+	reg = mfdcr(CPC0_CR0) & ~CR0_MASK;
 #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
 	clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
 	udiv = 1;
@@ -439,7 +439,7 @@
 #endif
 #endif
 	reg |= (udiv - 1) << CR0_UDIV_POS;	/* set the UART divisor */
-	mtdcr (cntrl0, reg);
+	mtdcr (CPC0_CR0, reg);
 #endif /* CONFIG_405EP */
 	tmp = gd->baudrate * udiv * 16;
 	bdiv = (clk + tmp / 2) / tmp;
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index e9861ab..2287904 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -64,7 +64,7 @@
 static int pci_async_enabled(void)
 {
 #if defined(CONFIG_405GP)
-	return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
+	return (mfdcr(CPC0_PSR) & PSR_PCI_ASYNC_EN);
 #endif
 
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
@@ -72,7 +72,7 @@
     defined(CONFIG_460EX) || defined(CONFIG_460GT)
 	unsigned long val;
 
-	mfsdr(sdr_sdstp1, val);
+	mfsdr(SDR0_SDSTP1, val);
 	return (val & SDR0_SDSTP1_PAME_MASK);
 #endif
 }
@@ -84,21 +84,21 @@
 static int pci_arbiter_enabled(void)
 {
 #if defined(CONFIG_405GP)
-	return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
+	return (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN);
 #endif
 
 #if defined(CONFIG_405EP)
-	return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
+	return (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN);
 #endif
 
 #if defined(CONFIG_440GP)
-	return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
+	return (mfdcr(CPC0_STRP1) & CPC0_STRP1_PAE_MASK);
 #endif
 
 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 	unsigned long val;
 
-	mfsdr(sdr_xcr, val);
+	mfsdr(SDR0_XCR, val);
 	return (val & 0x80000000);
 #endif
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
@@ -106,7 +106,7 @@
     defined(CONFIG_460EX) || defined(CONFIG_460GT)
 	unsigned long val;
 
-	mfsdr(sdr_pci0, val);
+	mfsdr(SDR0_PCI0, val);
 	return (val & 0x80000000);
 #endif
 }
@@ -118,11 +118,11 @@
 static int i2c_bootrom_enabled(void)
 {
 #if defined(CONFIG_405EP)
-	return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
+	return (mfdcr(CPC0_BOOT) & CPC0_BOOT_SEP);
 #else
 	unsigned long val;
 
-	mfsdr(sdr_sdcs, val);
+	mfsdr(SDR0_SDCS0, val);
 	return (val & SDR0_SDCS_SDD);
 #endif
 }
@@ -256,7 +256,7 @@
 {
 	unsigned long val;
 
-	mfsdr(SDR_PINSTP, val);
+	mfsdr(SDR0_PINSTP, val);
 	return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
 }
 #endif /* SDR0_PINSTP_SHIFT */
@@ -265,13 +265,13 @@
 #if defined(CONFIG_440)
 static int do_chip_reset (unsigned long sys0, unsigned long sys1)
 {
-	/* Changes to cpc0_sys0 and cpc0_sys1 require chip
+	/* Changes to CPC0_SYS0 and CPC0_SYS1 require chip
 	 * reset.
 	 */
-	mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000);	/* Set SWE */
-	mtdcr (cpc0_sys0, sys0);
-	mtdcr (cpc0_sys1, sys1);
-	mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000);	/* Clr SWE */
+	mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) | 0x80000000);	/* Set SWE */
+	mtdcr (CPC0_SYS0, sys0);
+	mtdcr (CPC0_SYS1, sys1);
+	mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) & ~0x80000000);	/* Clr SWE */
 	mtspr (SPRN_DBCR0, 0x20000000);	/* Reset the chip */
 
 	return 1;
@@ -410,13 +410,13 @@
 	case PVR_440GP_RB:
 		puts("GP Rev. B");
 		/* See errata 1.12: CHIP_4 */
-		if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
-		    (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
+		if ((mfdcr(CPC0_SYS0) != mfdcr(CPC0_STRP0)) ||
+		    (mfdcr(CPC0_SYS1) != mfdcr(CPC0_STRP1)) ){
 			puts (  "\n\t CPC0_SYSx DCRs corrupted. "
 				"Resetting chip ...\n");
 			udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
-			do_chip_reset ( mfdcr(cpc0_strp0),
-					mfdcr(cpc0_strp1) );
+			do_chip_reset ( mfdcr(CPC0_STRP0),
+					mfdcr(CPC0_STRP1) );
 		}
 		break;
 
diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index 65092fb..bd06b9b 100644
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -58,17 +58,17 @@
 		target_perdv0 = 4;
 		target_spcid0 = 4;
 
-		mfcpr(clk_primbd, reg);
+		mfcpr(CPR0_PRIMBD, reg);
 		temp = (reg & PRBDV_MASK) >> 24;
 		prbdv0 = temp ? temp : 8;
 		if (prbdv0 != target_prbdv0) {
 			reg &= ~PRBDV_MASK;
 			reg |= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24);
-			mtcpr(clk_primbd, reg);
+			mtcpr(CPR0_PRIMBD, reg);
 			reset_needed = 1;
 		}
 
-		mfcpr(clk_plld, reg);
+		mfcpr(CPR0_PLLD, reg);
 
 		temp = (reg & PLLD_FWDVA_MASK) >> 16;
 		fwdva = temp ? temp : 16;
@@ -89,35 +89,35 @@
 				((target_fwdvb == 8 ? 0 : target_fwdvb) << 8) |
 				((target_fbdv == 32 ? 0 : target_fbdv) << 24) |
 				(target_lfbdv == 64 ? 0 : target_lfbdv);
-			mtcpr(clk_plld, reg);
+			mtcpr(CPR0_PLLD, reg);
 			reset_needed = 1;
 		}
 
-		mfcpr(clk_perd, reg);
+		mfcpr(CPR0_PERD, reg);
 		perdv0 = (reg & CPR0_PERD_PERDV0_MASK) >> 24;
 		if (perdv0 != target_perdv0) {
 			reg &= ~CPR0_PERD_PERDV0_MASK;
 			reg |= (target_perdv0 << 24);
-			mtcpr(clk_perd, reg);
+			mtcpr(CPR0_PERD, reg);
 			reset_needed = 1;
 		}
 
-		mfcpr(clk_spcid, reg);
+		mfcpr(CPR0_SPCID, reg);
 		temp = (reg & CPR0_SPCID_SPCIDV0_MASK) >> 24;
 		spcid0 = temp ? temp : 4;
 		if (spcid0 != target_spcid0) {
 			reg &= ~CPR0_SPCID_SPCIDV0_MASK;
 			reg |= ((target_spcid0 == 4 ? 0 : target_spcid0) << 24);
-			mtcpr(clk_spcid, reg);
+			mtcpr(CPR0_SPCID, reg);
 			reset_needed = 1;
 		}
 
 		/* Set reload inhibit so configuration will persist across
 		 * processor resets */
-		mfcpr(clk_icfg, reg);
+		mfcpr(CPR0_ICFG, reg);
 		reg &= ~CPR0_ICFG_RLI_MASK;
 		reg |= 1 << 31;
-		mtcpr(clk_icfg, reg);
+		mtcpr(CPR0_ICFG, reg);
 	}
 
 	/* Reset processor if configuration changed */
@@ -173,7 +173,7 @@
 	/*
 	 * Set EMAC noise filter bits
 	 */
-	mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE);
+	mtdcr(CPC0_EPCTL, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE);
 #endif /* CONFIG_405EP */
 
 #if defined(CONFIG_SYS_4xx_GPIO_TABLE)
@@ -204,43 +204,43 @@
 	asm volatile("2:	bdnz	2b"		::: "ctr", "cr0");
 #endif
 
-	mtebc(pb0ap, CONFIG_SYS_EBC_PB0AP);
-	mtebc(pb0cr, CONFIG_SYS_EBC_PB0CR);
+	mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP);
+	mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR);
 #endif
 
 #if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 1))
-	mtebc(pb1ap, CONFIG_SYS_EBC_PB1AP);
-	mtebc(pb1cr, CONFIG_SYS_EBC_PB1CR);
+	mtebc(PB1AP, CONFIG_SYS_EBC_PB1AP);
+	mtebc(PB1CR, CONFIG_SYS_EBC_PB1CR);
 #endif
 
 #if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 2))
-	mtebc(pb2ap, CONFIG_SYS_EBC_PB2AP);
-	mtebc(pb2cr, CONFIG_SYS_EBC_PB2CR);
+	mtebc(PB2AP, CONFIG_SYS_EBC_PB2AP);
+	mtebc(PB2CR, CONFIG_SYS_EBC_PB2CR);
 #endif
 
 #if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 3))
-	mtebc(pb3ap, CONFIG_SYS_EBC_PB3AP);
-	mtebc(pb3cr, CONFIG_SYS_EBC_PB3CR);
+	mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP);
+	mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR);
 #endif
 
 #if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 4))
-	mtebc(pb4ap, CONFIG_SYS_EBC_PB4AP);
-	mtebc(pb4cr, CONFIG_SYS_EBC_PB4CR);
+	mtebc(PB4AP, CONFIG_SYS_EBC_PB4AP);
+	mtebc(PB4CR, CONFIG_SYS_EBC_PB4CR);
 #endif
 
 #if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 5))
-	mtebc(pb5ap, CONFIG_SYS_EBC_PB5AP);
-	mtebc(pb5cr, CONFIG_SYS_EBC_PB5CR);
+	mtebc(PB5AP, CONFIG_SYS_EBC_PB5AP);
+	mtebc(PB5CR, CONFIG_SYS_EBC_PB5CR);
 #endif
 
 #if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 6))
-	mtebc(pb6ap, CONFIG_SYS_EBC_PB6AP);
-	mtebc(pb6cr, CONFIG_SYS_EBC_PB6CR);
+	mtebc(PB6AP, CONFIG_SYS_EBC_PB6AP);
+	mtebc(PB6CR, CONFIG_SYS_EBC_PB6CR);
 #endif
 
 #if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 7))
-	mtebc(pb7ap, CONFIG_SYS_EBC_PB7AP);
-	mtebc(pb7cr, CONFIG_SYS_EBC_PB7CR);
+	mtebc(PB7AP, CONFIG_SYS_EBC_PB7AP);
+	mtebc(PB7CR, CONFIG_SYS_EBC_PB7CR);
 #endif
 
 #if defined (CONFIG_SYS_EBC_CFG)
@@ -276,9 +276,9 @@
 	 *       Compatibility mode and Ethernet Clock select are not
 	 *       correct in the manual
 	 */
-	mfsdr(sdr_mfr, val);
+	mfsdr(SDR0_MFR, val);
 	val &= ~0x10000000;
-	mtsdr(sdr_mfr,val);
+	mtsdr(SDR0_MFR,val);
 #endif /* CONFIG_440GX */
 
 #if defined(CONFIG_460EX)
@@ -304,10 +304,10 @@
 	/*
 	 * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
 	 */
-	mtdcr(plb0_acr, (mfdcr(plb0_acr) & ~plb0_acr_rdp_mask) |
-	      plb0_acr_rdp_4deep);
-	mtdcr(plb1_acr, (mfdcr(plb1_acr) & ~plb1_acr_rdp_mask) |
-	      plb1_acr_rdp_4deep);
+	mtdcr(PLB0_ACR, (mfdcr(PLB0_ACR) & ~PLB0_ACR_RDP_MASK) |
+	      PLB0_ACR_RDP_4DEEP);
+	mtdcr(PLB1_ACR, (mfdcr(PLB1_ACR) & ~PLB1_ACR_RDP_MASK) |
+	      PLB1_ACR_RDP_4DEEP);
 #endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
 }
 
@@ -324,7 +324,7 @@
 	 * for compatibility to existing PPC405GP designs.
 	 */
 	if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
-		mtdcr(ecr, 0x60606000);
+		mtdcr(CPC0_ECR, 0x60606000);
 	}
 #endif  /* defined(CONFIG_405GP) */
 
diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c
index ba5c120..496e028 100644
--- a/cpu/ppc4xx/fdt.c
+++ b/cpu/ppc4xx/fdt.c
@@ -51,8 +51,8 @@
 	 * peripheral banks into the OPB/PLB address space
 	 */
 	for (i = 0; i < EBC_NUM_BANKS; i++) {
-		mtdcr(ebccfga, EBC_BXCR(i));
-		bxcr = mfdcr(ebccfgd);
+		mtdcr(EBC0_CFGADDR, EBC_BXCR(i));
+		bxcr = mfdcr(EBC0_CFGDATA);
 
 		if ((bxcr & EBC_BXCR_BU_MASK) != EBC_BXCR_BU_NONE) {
 			*p++ = i;
diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c
index 4365df9..5a3336e 100644
--- a/cpu/ppc4xx/sdram.c
+++ b/cpu/ppc4xx/sdram.c
@@ -375,8 +375,8 @@
 	/*
 	 * Soft-reset SDRAM controller.
 	 */
-	mtsdr(sdr_srst, SDR0_SRST_DMC);
-	mtsdr(sdr_srst, 0x00000000);
+	mtsdr(SDR0_SRST, SDR0_SRST_DMC);
+	mtsdr(SDR0_SRST, 0x00000000);
 #endif
 
 	for (i=0; i<N_MB0CF; i++) {
diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c
index c0a5824..1f75137 100644
--- a/cpu/ppc4xx/speed.c
+++ b/cpu/ppc4xx/speed.c
@@ -50,12 +50,12 @@
 	/*
 	 * Read PLL Mode register
 	 */
-	pllmr = mfdcr (pllmd);
+	pllmr = mfdcr (CPC0_PLLMR);
 
 	/*
 	 * Read Pin Strapping register
 	 */
-	psr = mfdcr (strap);
+	psr = mfdcr (CPC0_PSR);
 
 	/*
 	 * Determine FWD_DIV.
@@ -280,8 +280,8 @@
 	unsigned long plbedv0;
 
 	/* Extract configured divisors */
-	mfsdr(sdr_sdstp0, strp0);
-	mfsdr(sdr_sdstp1, strp1);
+	mfsdr(SDR0_SDSTP0, strp0);
+	mfsdr(SDR0_SDSTP1, strp1);
 
 	temp = ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 4);
 	sysInfo->pllFwdDivA = get_cpr0_fwdv(temp);
@@ -342,7 +342,7 @@
 	*/
 
 	/* Decode CPR0_PLLD0 for divisors */
-	mfcpr(clk_plld, reg);
+	mfcpr(CPR0_PLLD, reg);
 	temp = (reg & PLLD_FWDVA_MASK) >> 16;
 	sysInfo->pllFwdDivA = temp ? temp : 16;
 	temp = (reg & PLLD_FWDVB_MASK) >> 8;
@@ -351,28 +351,28 @@
 	sysInfo->pllFbkDiv = temp ? temp : 32;
 	lfdiv = reg & PLLD_LFBDV_MASK;
 
-	mfcpr(clk_opbd, reg);
+	mfcpr(CPR0_OPBD, reg);
 	temp = (reg & OPBDDV_MASK) >> 24;
 	sysInfo->pllOpbDiv = temp ? temp : 4;
 
-	mfcpr(clk_perd, reg);
+	mfcpr(CPR0_PERD, reg);
 	temp = (reg & PERDV_MASK) >> 24;
 	sysInfo->pllExtBusDiv = temp ? temp : 8;
 
-	mfcpr(clk_primbd, reg);
+	mfcpr(CPR0_PRIMBD, reg);
 	temp = (reg & PRBDV_MASK) >> 24;
 	prbdv0 = temp ? temp : 8;
 
-	mfcpr(clk_spcid, reg);
+	mfcpr(CPR0_SPCID, reg);
 	temp = (reg & SPCID_MASK) >> 24;
 	sysInfo->pllPciDiv = temp ? temp : 4;
 
 	/* Calculate 'M' based on feedback source */
-	mfsdr(sdr_sdstp0, reg);
+	mfsdr(SDR0_SDSTP0, reg);
 	temp = (reg & PLLSYS0_SEL_MASK) >> 27;
 	if (temp == 0) { /* PLL output */
 		/* Figure which pll to use */
-		mfcpr(clk_pllc, reg);
+		mfcpr(CPR0_PLLC, reg);
 		temp = (reg & PLLC_SRC_MASK) >> 29;
 		if (!temp) /* PLLOUTA */
 			m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA;
@@ -426,7 +426,7 @@
 	unsigned long m;
 
 	/* Extract configured divisors */
-	strp0 = mfdcr( cpc0_strp0 );
+	strp0 = mfdcr( CPC0_STRP0 );
 	sysInfo->pllFwdDivA = 8 - ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 15);
 	sysInfo->pllFwdDivB = 8 - ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 12);
 	temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 18;
@@ -484,8 +484,8 @@
 #endif
 
 	/* Extract configured divisors */
-	mfsdr( sdr_sdstp0,strp0 );
-	mfsdr( sdr_sdstp1,strp1 );
+	mfsdr( SDR0_SDSTP0,strp0 );
+	mfsdr( SDR0_SDSTP1,strp1 );
 
 	temp = ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 8);
 	sysInfo->pllFwdDivA = temp ? temp : 16 ;
@@ -531,7 +531,7 @@
 	/* Determine PCI Clock Period */
 	pci_clock_per = determine_pci_clock_per();
 	sysInfo->freqPCI = (ONE_BILLION/pci_clock_per) * 1000;
-	mfsdr(sdr_ddr0, sdr_ddrpll);
+	mfsdr(SDR0_DDR0, sdr_ddrpll);
 	sysInfo->freqDDR = ((sysInfo->freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
 #endif
 
@@ -794,8 +794,8 @@
 	/*
 	 * Read PLL Mode registers
 	 */
-	pllmr0 = mfdcr (cpc0_pllmr0);
-	pllmr1 = mfdcr (cpc0_pllmr1);
+	pllmr0 = mfdcr (CPC0_PLLMR0);
+	pllmr1 = mfdcr (CPC0_PLLMR1);
 
 	/*
 	 * Determine forward divider A
@@ -918,8 +918,8 @@
 	/*
 	 * Read PLL Mode registers
 	 */
-	mfcpr(cprplld, cpr_plld);
-	mfcpr(cprpllc, cpr_pllc);
+	mfcpr(CPR0_PLLD, cpr_plld);
+	mfcpr(CPR0_PLLC, cpr_pllc);
 
 	/*
 	 * Determine forward divider A
@@ -943,7 +943,7 @@
 	/*
 	 * Read CPR_PRIMAD register
 	 */
-	mfcpr(cprprimad, cpr_primad);
+	mfcpr(CPC0_PRIMAD, cpr_primad);
 
 	/*
 	 * Determine PLB_DIV.
@@ -1074,7 +1074,7 @@
 	};
 	unsigned char sel, cpudv0, plb2xDiv;
 
-	mfcpr(cpr0_plld, tmp);
+	mfcpr(CPR0_PLLD, tmp);
 
 	/*
 	 * Determine forward divider A
@@ -1094,29 +1094,29 @@
 	/*
 	 * Determine PERDV0
 	 */
-	mfcpr(cpr0_perd, tmp);
+	mfcpr(CPR0_PERD, tmp);
 	tmp = (tmp >> 24) & 0x03;
 	sysInfo->pllExtBusDiv = (tmp == 0) ? 4 : tmp;
 
 	/*
 	 * Determine OPBDV0
 	 */
-	mfcpr(cpr0_opbd, tmp);
+	mfcpr(CPR0_OPBD, tmp);
 	tmp = (tmp >> 24) & 0x03;
 	sysInfo->pllOpbDiv = (tmp == 0) ? 4 : tmp;
 
 	/* Determine PLB2XDV0 */
-	mfcpr(cpr0_plbd, tmp);
+	mfcpr(CPR0_PLBD, tmp);
 	tmp = (tmp >> 16) & 0x07;
 	plb2xDiv = (tmp == 0) ? 8 : tmp;
 
 	/* Determine CPUDV0 */
-	mfcpr(cpr0_cpud, tmp);
+	mfcpr(CPR0_CPUD, tmp);
 	tmp = (tmp >> 24) & 0x07;
 	cpudv0 = (tmp == 0) ? 8 : tmp;
 
 	/* Determine SEL(5:7) in CPR0_PLLC */
-	mfcpr(cpr0_pllc, tmp);
+	mfcpr(CPR0_PLLC, tmp);
 	sel = (tmp >> 24) & 0x07;
 
 	/*
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index f967d84..287a912 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -83,64 +83,64 @@
 
 #ifdef CONFIG_SYS_INIT_DCACHE_CS
 # if (CONFIG_SYS_INIT_DCACHE_CS == 0)
-#  define PBxAP pb0ap
-#  define PBxCR pb0cr
+#  define PBxAP PB1AP
+#  define PBxCR PB0CR
 #  if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
 #   define PBxAP_VAL CONFIG_SYS_EBC_PB0AP
 #   define PBxCR_VAL CONFIG_SYS_EBC_PB0CR
 #  endif
 # endif
 # if (CONFIG_SYS_INIT_DCACHE_CS == 1)
-#  define PBxAP pb1ap
-#  define PBxCR pb1cr
+#  define PBxAP PB1AP
+#  define PBxCR PB1CR
 #  if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR))
 #   define PBxAP_VAL CONFIG_SYS_EBC_PB1AP
 #   define PBxCR_VAL CONFIG_SYS_EBC_PB1CR
 #  endif
 # endif
 # if (CONFIG_SYS_INIT_DCACHE_CS == 2)
-#  define PBxAP pb2ap
-#  define PBxCR pb2cr
+#  define PBxAP PB2AP
+#  define PBxCR PB2CR
 #  if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR))
 #   define PBxAP_VAL CONFIG_SYS_EBC_PB2AP
 #   define PBxCR_VAL CONFIG_SYS_EBC_PB2CR
 #  endif
 # endif
 # if (CONFIG_SYS_INIT_DCACHE_CS == 3)
-#  define PBxAP pb3ap
-#  define PBxCR pb3cr
+#  define PBxAP PB3AP
+#  define PBxCR PB3CR
 #  if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR))
 #   define PBxAP_VAL CONFIG_SYS_EBC_PB3AP
 #   define PBxCR_VAL CONFIG_SYS_EBC_PB3CR
 #  endif
 # endif
 # if (CONFIG_SYS_INIT_DCACHE_CS == 4)
-#  define PBxAP pb4ap
-#  define PBxCR pb4cr
+#  define PBxAP PB4AP
+#  define PBxCR PB4CR
 #  if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR))
 #   define PBxAP_VAL CONFIG_SYS_EBC_PB4AP
 #   define PBxCR_VAL CONFIG_SYS_EBC_PB4CR
 #  endif
 # endif
 # if (CONFIG_SYS_INIT_DCACHE_CS == 5)
-#  define PBxAP pb5ap
-#  define PBxCR pb5cr
+#  define PBxAP PB5AP
+#  define PBxCR PB5CR
 #  if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR))
 #   define PBxAP_VAL CONFIG_SYS_EBC_PB5AP
 #   define PBxCR_VAL CONFIG_SYS_EBC_PB5CR
 #  endif
 # endif
 # if (CONFIG_SYS_INIT_DCACHE_CS == 6)
-#  define PBxAP pb6ap
-#  define PBxCR pb6cr
+#  define PBxAP PB6AP
+#  define PBxCR PB6CR
 #  if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR))
 #   define PBxAP_VAL CONFIG_SYS_EBC_PB6AP
 #   define PBxCR_VAL CONFIG_SYS_EBC_PB6CR
 #  endif
 # endif
 # if (CONFIG_SYS_INIT_DCACHE_CS == 7)
-#  define PBxAP pb7ap
-#  define PBxCR pb7cr
+#  define PBxAP PB7AP
+#  define PBxCR PB7CR
 #  if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR))
 #   define PBxAP_VAL CONFIG_SYS_EBC_PB7AP
 #   define PBxCR_VAL CONFIG_SYS_EBC_PB7CR
@@ -998,7 +998,7 @@
 	/*----------------------------------------------------------------------- */
 	addis	r3,r0, 0xFFFF		/* Clear all existing DMA status */
 	ori	r3,r3, 0xFFFF
-	mtdcr	dmasr, r3
+	mtdcr	DMASR, r3
 
 	bl	ppc405ep_init		/* do ppc405ep specific init */
 #endif /* CONFIG_405EP */
@@ -1015,21 +1015,21 @@
 	lis	r3,CONFIG_SYS_OCM_DATA_ADDR@h	/* OCM location */
 	ori	r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
 	ori	r3,r3,0x0270		/* 16K for Bank 1, R/W/Enable */
-	mtdcr	ocmplb3cr1,r3		/* Set PLB Access */
+	mtdcr	OCM0_PLBCR1,r3		/* Set PLB Access */
 	ori	r3,r3,0x4000		/* Add 0x4000 for bank 2 */
-	mtdcr	ocmplb3cr2,r3		/* Set PLB Access */
+	mtdcr	OCM0_PLBCR2,r3		/* Set PLB Access */
 	isync
 
 	lis	r3,CONFIG_SYS_OCM_DATA_ADDR@h	/* OCM location */
 	ori	r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
 	ori	r3,r3,0x0270		/* 16K for Bank 1, R/W/Enable */
-	mtdcr	ocmdscr1, r3		/* Set Data Side */
-	mtdcr	ocmiscr1, r3		/* Set Instruction Side */
+	mtdcr	OCM0_DSRC1, r3		/* Set Data Side */
+	mtdcr	OCM0_ISRC1, r3		/* Set Instruction Side */
 	ori	r3,r3,0x4000		/* Add 0x4000 for bank 2 */
-	mtdcr	ocmdscr2, r3		/* Set Data Side */
-	mtdcr	ocmiscr2, r3		/* Set Instruction Side */
+	mtdcr	OCM0_DSRC2, r3		/* Set Data Side */
+	mtdcr	OCM0_ISRC2, r3		/* Set Instruction Side */
 	addis	r3,0,0x0800		/* OCM Data Parity Disable - 1 Wait State */
-	mtdcr	ocmdsisdpc,r3
+	mtdcr	OCM0_DISDPC,r3
 
 	isync
 #else /* CONFIG_405EZ */
@@ -1039,19 +1039,19 @@
 	/* Setup OCM */
 	lis	r0, 0x7FFF
 	ori	r0, r0, 0xFFFF
-	mfdcr	r3, ocmiscntl		/* get instr-side IRAM config */
-	mfdcr	r4, ocmdscntl		/* get data-side IRAM config */
+	mfdcr	r3, OCM0_ISCNTL		/* get instr-side IRAM config */
+	mfdcr	r4, OCM0_DSCNTL		/* get data-side IRAM config */
 	and	r3, r3, r0		/* disable data-side IRAM */
 	and	r4, r4, r0		/* disable data-side IRAM */
-	mtdcr	ocmiscntl, r3		/* set instr-side IRAM config */
-	mtdcr	ocmdscntl, r4		/* set data-side IRAM config */
+	mtdcr	OCM0_ISCNTL, r3		/* set instr-side IRAM config */
+	mtdcr	OCM0_DSCNTL, r4		/* set data-side IRAM config */
 	isync
 
 	lis	r3,CONFIG_SYS_OCM_DATA_ADDR@h	/* OCM location */
 	ori	r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
-	mtdcr	ocmdsarc, r3
+	mtdcr	OCM0_DSARC, r3
 	addis	r4, 0, 0xC000		/* OCM data area enabled */
-	mtdcr	ocmdscntl, r4
+	mtdcr	OCM0_DSCNTL, r4
 	isync
 #endif /* CONFIG_405EZ */
 #endif
@@ -1061,16 +1061,16 @@
 	/*----------------------------------------------------------------------- */
 #ifdef CONFIG_SYS_INIT_DCACHE_CS
 	li	r4, PBxAP
-	mtdcr	ebccfga, r4
+	mtdcr	EBC0_CFGADDR, r4
 	lis	r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h
 	ori	r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l
-	mtdcr	ebccfgd, r4
+	mtdcr	EBC0_CFGDATA, r4
 
 	addi	r4, 0, PBxCR
-	mtdcr	ebccfga, r4
+	mtdcr	EBC0_CFGADDR, r4
 	lis	r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h
 	ori	r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l
-	mtdcr	ebccfgd, r4
+	mtdcr	EBC0_CFGDATA, r4
 
 	/*
 	 * Enable the data cache for the 128MB storage access control region
@@ -1428,16 +1428,16 @@
 
 	/* Restore the EBC parameters */
 	li	r3, PBxAP
-	mtdcr	ebccfga, r3
+	mtdcr	EBC0_CFGADDR, r3
 	lis	r3, PBxAP_VAL@h
 	ori	r3, r3, PBxAP_VAL@l
-	mtdcr	ebccfgd, r3
+	mtdcr	EBC0_CFGDATA, r3
 
 	li	r3, PBxCR
-	mtdcr	ebccfga, r3
+	mtdcr	EBC0_CFGADDR, r3
 	lis	r3, PBxCR_VAL@h
 	ori	r3, r3, PBxCR_VAL@l
-	mtdcr	ebccfgd, r3
+	mtdcr	EBC0_CFGDATA, r3
 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
 
 	/* Restore registers */
@@ -1860,38 +1860,38 @@
 	ori	r4,r4,CONFIG_SYS_GPIO0_TCR@l
 	stw	r4,0(r3)
 
-	li	r3,pb1ap		/* program EBC bank 1 for RTC access */
-	mtdcr	ebccfga,r3
+	li	r3,PB1AP		/* program EBC bank 1 for RTC access */
+	mtdcr	EBC0_CFGADDR,r3
 	lis	r3,CONFIG_SYS_EBC_PB1AP@h
 	ori	r3,r3,CONFIG_SYS_EBC_PB1AP@l
-	mtdcr	ebccfgd,r3
-	li	r3,pb1cr
-	mtdcr	ebccfga,r3
+	mtdcr	EBC0_CFGDATA,r3
+	li	r3,PB1CR
+	mtdcr	EBC0_CFGADDR,r3
 	lis	r3,CONFIG_SYS_EBC_PB1CR@h
 	ori	r3,r3,CONFIG_SYS_EBC_PB1CR@l
-	mtdcr	ebccfgd,r3
+	mtdcr	EBC0_CFGDATA,r3
 
-	li	r3,pb1ap		/* program EBC bank 1 for RTC access */
-	mtdcr	ebccfga,r3
+	li	r3,PB1AP		/* program EBC bank 1 for RTC access */
+	mtdcr	EBC0_CFGADDR,r3
 	lis	r3,CONFIG_SYS_EBC_PB1AP@h
 	ori	r3,r3,CONFIG_SYS_EBC_PB1AP@l
-	mtdcr	ebccfgd,r3
-	li	r3,pb1cr
-	mtdcr	ebccfga,r3
+	mtdcr	EBC0_CFGDATA,r3
+	li	r3,PB1CR
+	mtdcr	EBC0_CFGADDR,r3
 	lis	r3,CONFIG_SYS_EBC_PB1CR@h
 	ori	r3,r3,CONFIG_SYS_EBC_PB1CR@l
-	mtdcr	ebccfgd,r3
+	mtdcr	EBC0_CFGDATA,r3
 
-	li	r3,pb4ap		/* program EBC bank 4 for FPGA access */
-	mtdcr	ebccfga,r3
+	li	r3,PB4AP		/* program EBC bank 4 for FPGA access */
+	mtdcr	EBC0_CFGADDR,r3
 	lis	r3,CONFIG_SYS_EBC_PB4AP@h
 	ori	r3,r3,CONFIG_SYS_EBC_PB4AP@l
-	mtdcr	ebccfgd,r3
-	li	r3,pb4cr
-	mtdcr	ebccfga,r3
+	mtdcr	EBC0_CFGDATA,r3
+	li	r3,PB4CR
+	mtdcr	EBC0_CFGADDR,r3
 	lis	r3,CONFIG_SYS_EBC_PB4CR@h
 	ori	r3,r3,CONFIG_SYS_EBC_PB4CR@l
-	mtdcr	ebccfgd,r3
+	mtdcr	EBC0_CFGDATA,r3
 #endif
 
 	/*
diff --git a/cpu/ppc4xx/usbdev.c b/cpu/ppc4xx/usbdev.c
index faf7f08..5bb4f3c 100644
--- a/cpu/ppc4xx/usbdev.c
+++ b/cpu/ppc4xx/usbdev.c
@@ -206,14 +206,14 @@
 #ifdef USB_2_0_DEVICE
 	printf("USB 2.0 Device init\n");
 	/*select 2.0 device */
-	mtsdr(sdr_usb0, 0x0);	/* 2.0 */
+	mtsdr(SDR0_USB0, 0x0);	/* 2.0 */
 
 	/*usb dev init */
 	*(unsigned char *)USB2D0_POWER_8 = 0xa1;	/* 2.0 */
 #else
 	printf("USB 1.1 Device init\n");
 	/*select 1.1 device */
-	mtsdr(sdr_usb0, 0x2);	/* 1.1 */
+	mtsdr(SDR0_USB0, 0x2);	/* 1.1 */
 
 	/*usb dev init */
 	*(unsigned char *)USB2D0_POWER_8 = 0xc0;	/* 1.1 */