ARM: mx6: ddr: Add support for iMX6UL/ULL/SL/SDL
This patch adds support for iMX6UL/ULL/SL/SDL MMDC into the DDR calibration
code. The difference between MX6DQ and MX6UL/ULL/SL is that the later SoCs
have 2 SDQS registers, just like MX6SX, while the MX6DQ/MX6SDL has 8.
Fixes: 4f4c128c65 ("ARM: mx6: ddr: Add support for iMX6SX")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eric Nelson <eric@nelint.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c
index 16df710..f872bfd 100644
--- a/arch/arm/mach-imx/mx6/ddr.c
+++ b/arch/arm/mach-imx/mx6/ddr.c
@@ -250,16 +250,31 @@
static void mmdc_set_sdqs(bool set)
{
+ struct mx6sdl_iomux_ddr_regs *mx6sdl_ddr_iomux =
+ (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE;
struct mx6dq_iomux_ddr_regs *mx6dq_ddr_iomux =
(struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
struct mx6sx_iomux_ddr_regs *mx6sx_ddr_iomux =
(struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
+ struct mx6sl_iomux_ddr_regs *mx6sl_ddr_iomux =
+ (struct mx6sl_iomux_ddr_regs *)MX6SL_IOM_DDR_BASE;
+ struct mx6ul_iomux_ddr_regs *mx6ul_ddr_iomux =
+ (struct mx6ul_iomux_ddr_regs *)MX6UL_IOM_DDR_BASE;
int i, sdqs_cnt;
u32 sdqs;
if (is_mx6sx()) {
sdqs = (u32)(&mx6sx_ddr_iomux->dram_sdqs0);
sdqs_cnt = 2;
+ } else if (is_mx6sl()) {
+ sdqs = (u32)(&mx6sl_ddr_iomux->dram_sdqs0);
+ sdqs_cnt = 2;
+ } else if (is_mx6ul() || is_mx6ull()) {
+ sdqs = (u32)(&mx6ul_ddr_iomux->dram_sdqs0);
+ sdqs_cnt = 2;
+ } else if (is_mx6sdl()) {
+ sdqs = (u32)(&mx6sdl_ddr_iomux->dram_sdqs0);
+ sdqs_cnt = 8;
} else { /* MX6DQ */
sdqs = (u32)(&mx6dq_ddr_iomux->dram_sdqs0);
sdqs_cnt = 8;