mx31: define pins and init for UART2 and CSPI3
Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
Acked-by: Stefano Babic <sbabic@denx.de>
diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
index 6ce008d..f487975 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -680,12 +680,23 @@
/* Register offsets based on IOMUXC_BASE */
/* 0x00 .. 0x7b */
+#define MUX_CTL_CSPI3_MISO 0x0c
+#define MUX_CTL_CSPI3_SCLK 0x0d
+#define MUX_CTL_CSPI3_SPI_RDY 0x0e
+#define MUX_CTL_CSPI3_MOSI 0x13
+
#define MUX_CTL_USBH2_DATA1 0x40
#define MUX_CTL_USBH2_DIR 0x44
#define MUX_CTL_USBH2_STP 0x45
#define MUX_CTL_USBH2_NXT 0x46
#define MUX_CTL_USBH2_DATA0 0x47
#define MUX_CTL_USBH2_CLK 0x4B
+
+#define MUX_CTL_TXD2 0x70
+#define MUX_CTL_RTS2 0x71
+#define MUX_CTL_CTS2 0x72
+#define MUX_CTL_RXD2 0x77
+
#define MUX_CTL_RTS1 0x7c
#define MUX_CTL_CTS1 0x7d
#define MUX_CTL_DTR_DCE1 0x7e
@@ -743,6 +754,11 @@
#define MUX_RTS1__UART1_RTS_B IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC)
#define MUX_CTS1__UART1_CTS_B IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC)
+#define MUX_RXD2__UART2_RXD_MUX IOMUX_MODE(MUX_CTL_RXD2, MUX_CTL_FUNC)
+#define MUX_TXD2__UART2_TXD_MUX IOMUX_MODE(MUX_CTL_TXD2, MUX_CTL_FUNC)
+#define MUX_RTS2__UART2_RTS_B IOMUX_MODE(MUX_CTL_RTS2, MUX_CTL_FUNC)
+#define MUX_CTS2__UART2_CTS_B IOMUX_MODE(MUX_CTL_CTS2, MUX_CTL_FUNC)
+
#define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC)
#define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC)
#define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC)