Tegra: Configure L2 cache control reg properly.
Without this change, kernel fails at calling function cache_clean_flush
during kernel early boot.
Aprocryphally, intended for T114 only, so I check for a T114 SoC.
Works (i.e. dalmore 3.8 kernel now starts printing to console).
Signed-off-by: Tom Warren <twarren@nvidia.com>
diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c
index 3f30805..a739fe2 100644
--- a/arch/arm/cpu/tegra-common/ap.c
+++ b/arch/arm/cpu/tegra-common/ap.c
@@ -139,11 +139,6 @@
enable_scu();
- /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
- asm volatile(
- "mrc p15, 0, r0, c1, c0, 1\n"
- "orr r0, r0, #0x41\n"
- "mcr p15, 0, r0, c1, c0, 1\n");
-
- /* FIXME: should have SoC's L2 disabled too? */
+ /* init the cache */
+ config_cache();
}