Update MTD to that of Linux 2.6.22.1
A lot changed in the Linux MTD code, since it was last ported from
Linux to U-Boot. This patch takes U-Boot NAND support to the level
of Linux 2.6.22.1 and will enable support for very large NAND devices
(4KB pages) and ease the compatibility between U-Boot and Linux
filesystems.
This patch is tested on two custom boards with PPC and ARM
processors running YAFFS in U-Boot and Linux using gcc-4.1.2
cross compilers.
MAKEALL ppc/arm has some issues:
* DOC/OneNand/nand_spl is not building (I have not tried porting
these parts, and since I do not have any HW and I am not familiar
with this code/HW I think its best left to someone else.)
Except for the issues mentioned above, I have ported all drivers
necessary to run MAKEALL ppc/arm without errors and warnings. Many
drivers were trivial to port, but some were not so trivial. The
following drivers must be examined carefully and maybe rewritten to
some degree:
cpu/ppc4xx/ndfc.c
cpu/arm926ejs/davinci/nand.c
board/delta/nand.c
board/zylonite/nand.c
Signed-off-by: William Juul <william.juul@tandberg.com>
Signed-off-by: Stig Olsen <stig.olsen@tandberg.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
diff --git a/board/sc3/sc3nand.c b/board/sc3/sc3nand.c
index 009567b..2f2e745 100644
--- a/board/sc3/sc3nand.c
+++ b/board/sc3/sc3nand.c
@@ -39,30 +39,26 @@
static void *sc3_io_base;
static void *sc3_control_base = (void *)0xEF600700;
-static void sc3_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+static void sc3_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
- switch (cmd) {
- case NAND_CTL_SETCLE:
- set_bit (SC3_NAND_CLE, sc3_control_base);
- break;
- case NAND_CTL_CLRCLE:
- clear_bit (SC3_NAND_CLE, sc3_control_base);
- break;
-
- case NAND_CTL_SETALE:
- set_bit (SC3_NAND_ALE, sc3_control_base);
- break;
- case NAND_CTL_CLRALE:
- clear_bit (SC3_NAND_ALE, sc3_control_base);
- break;
-
- case NAND_CTL_SETNCE:
- set_bit (SC3_NAND_CE, sc3_control_base);
- break;
- case NAND_CTL_CLRNCE:
- clear_bit (SC3_NAND_CE, sc3_control_base);
- break;
+ struct nand_chip *this = mtd->priv;
+ if (ctrl & NAND_CTRL_CHANGE) {
+ if ( ctrl & NAND_CLE )
+ set_bit (SC3_NAND_CLE, sc3_control_base);
+ else
+ clear_bit (SC3_NAND_CLE, sc3_control_base);
+ if ( ctrl & NAND_ALE )
+ set_bit (SC3_NAND_ALE, sc3_control_base);
+ else
+ clear_bit (SC3_NAND_ALE, sc3_control_base);
+ if ( ctrl & NAND_NCE )
+ set_bit (SC3_NAND_CE, sc3_control_base);
+ else
+ clear_bit (SC3_NAND_CE, sc3_control_base);
}
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
}
static int sc3_nand_dev_ready(struct mtd_info *mtd)
@@ -79,14 +75,14 @@
int board_nand_init(struct nand_chip *nand)
{
- nand->eccmode = NAND_ECC_SOFT;
+ nand->ecc.mode = NAND_ECC_SOFT;
sc3_io_base = (void *) CFG_NAND_BASE;
/* Set address of NAND IO lines (Using Linear Data Access Region) */
nand->IO_ADDR_R = (void __iomem *) sc3_io_base;
nand->IO_ADDR_W = (void __iomem *) sc3_io_base;
/* Reference hardware control function */
- nand->hwcontrol = sc3_nand_hwcontrol;
+ nand->cmd_ctrl = sc3_nand_hwcontrol;
nand->dev_ready = sc3_nand_dev_ready;
nand->select_chip = sc3_select_chip;
return 0;