xilinx: Add env redund offset
ENV_OFFSET_REDUND config is by default set to 0 for flashes. Saving the env
variables is overwriting data at 0 offset, which is wrong. So add default
redund env offset for Zynq, ZynqMP, Versal and microblaze platforms.
Configured ENV_OFFSET_REDUND offsets by ENV_OFFSET + (2 * ENV_SIZE).
In case of versal, we configured ENV_OFFSET_REDUND at 0x7F00000 instead
of 0x7F80000. As BOOT_SCRIPT_OFFSET is already configured at 0x7F80000.
Added ENV_OFFSET_REDUND in Kconfig for microblaze due to dependency of
ENV_IS_IN_SPI_FLASH config.
Below table specifies platform specific env and env redund offsets.
PLAT ENV_OFFSET ENV_OFFSET_REDUND
---- ---------- -----------------
ZYNQ 0xE0000 0xE40000
ZYNQMP 0x1E00000 0x1E80000
VERSAL 0x7F40000 0x7F00000
MICROBLAZE 0x1080000 0x10C0000
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/92656dc08f0f5a749d62b71ca6e77fe1be72e9e0.1661340204.git.michal.simek@amd.com
diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index e5ac26e..e242884 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_SIZE_LIMIT=0x2a000
CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x0
CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0x1E80000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_ZYNQ_MAC_IN_EEPROM=y