Merge tag 'u-boot-dfu-20240910' of https://source.denx.de/u-boot/custodians/u-boot-dfu
CI: https://source.denx.de/u-boot/custodians/u-boot-dfu/-/pipelines/22302
- Fix ANDROID_AB_BACKUP_OFFSET unit
diff --git a/arch/arm/dts/imx8mq-u-boot.dtsi b/arch/arm/dts/imx8mq-u-boot.dtsi
index e1cd6f8..9b895a6 100644
--- a/arch/arm/dts/imx8mq-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-u-boot.dtsi
@@ -111,6 +111,8 @@
#endif
#address-cells = <1>;
+ offset = <0x57c00>;
+
images {
uboot {
arch = "arm64";
diff --git a/arch/arm/dts/r8a779g0-u-boot.dtsi b/arch/arm/dts/r8a779g0-u-boot.dtsi
index cc8beca..f60eba5 100644
--- a/arch/arm/dts/r8a779g0-u-boot.dtsi
+++ b/arch/arm/dts/r8a779g0-u-boot.dtsi
@@ -8,7 +8,6 @@
#include "r8a779x-u-boot.dtsi"
&rpc {
- reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>;
bank-width = <2>;
num-cs = <1>;
};
diff --git a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi
index a102639..c3704d7 100644
--- a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi
+++ b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi
@@ -13,29 +13,9 @@
};
};
-&pfc {
- qspi0_pins: qspi0 {
- groups = "qspi0_ctrl", "qspi0_data4";
- function = "qspi0";
- };
-};
-
&rpc {
- pinctrl-0 = <&qspi0_pins>;
- pinctrl-names = "default";
-
- #address-cells = <1>;
- #size-cells = <0>;
- spi-max-frequency = <40000000>;
- status = "disabled";
-
- spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "s25fs512s", "jedec,spi-nor";
- reg = <0>;
+ flash@0 {
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
- spi-max-frequency = <40000000>;
};
};
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 4a83287..c1a1a33 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -149,6 +149,7 @@
select SPL_SYS_MALLOC_SIMPLE
select SYS_I2C_MVTWSI
select ATSHA204A
+ select I2C_EEPROM
select ARMADA_38X_SUPPORT_OLD_DDR3_TRAINING
config TARGET_TURRIS_MOX
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index fa3b016..876bec3 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -133,6 +133,7 @@
config SPL_FRAMEPOINTER
bool "Build SPL with frame pointer for stack unwinding"
+ depends on SPL
help
Choose this option to use the frame pointer so the stack can be
unwound if needed. This is useful for tracing where faults came
@@ -437,7 +438,20 @@
If disable this, it will send IPI by CPUs node numbers of device tree.
config SHOW_REGS
+ default y
bool "Show registers on unhandled exception"
+ help
+ By default only the program counter and the return address register
+ are shown in crash dumps. Enable this symbol to show all registers in
+ main U-Boot.
+
+config SPL_SHOW_REGS
+ bool "In SPL show registers on unhandled exception"
+ depends on SPL
+ help
+ By default only the program counter and the return address register
+ are shown in crash dumps. Enable this symbol to show all registers in
+ SPL.
config RISCV_PRIV_1_9
bool "Use version 1.9 of the RISC-V priviledged specification"
diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitops.h
index 35f1368..2f2994c 100644
--- a/arch/riscv/include/asm/bitops.h
+++ b/arch/riscv/include/asm/bitops.h
@@ -138,6 +138,43 @@
return k;
}
+static inline int find_next_zero_bit(void *addr, int size, int offset)
+{
+ unsigned long *p = ((unsigned long *)addr) + (offset / BITS_PER_LONG);
+ unsigned long result = offset & ~(BITS_PER_LONG - 1);
+ unsigned long tmp;
+
+ if (offset >= size)
+ return size;
+ size -= result;
+ offset &= (BITS_PER_LONG - 1);
+ if (offset) {
+ tmp = *(p++);
+ tmp |= ~0UL >> (BITS_PER_LONG - offset);
+ if (size < BITS_PER_LONG)
+ goto found_first;
+ if (~tmp)
+ goto found_middle;
+ size -= BITS_PER_LONG;
+ result += BITS_PER_LONG;
+ }
+ while (size & ~(BITS_PER_LONG - 1)) {
+ tmp = *(p++);
+ if (~tmp)
+ goto found_middle;
+ result += BITS_PER_LONG;
+ size -= BITS_PER_LONG;
+ }
+ if (!size)
+ return result;
+ tmp = *p;
+
+found_first:
+ tmp |= ~0UL << size;
+found_middle:
+ return result + ffz(tmp);
+}
+
/*
* ffs: find first bit set. This is defined the same way as
* the libc and compiler builtin ffs routines, therefore
@@ -158,6 +195,9 @@
#define hweight16(x) generic_hweight16(x)
#define hweight8(x) generic_hweight8(x)
+#define find_first_zero_bit(addr, size) \
+ find_next_zero_bit((addr), (size), 0)
+
#define test_and_set_bit __test_and_set_bit
#define test_and_clear_bit __test_and_clear_bit
diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index f9a1428..714cc92 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -34,9 +34,8 @@
efi_print_image_infos((void *)epc);
}
-static void show_regs(struct pt_regs *regs)
+static void __maybe_unused show_regs(struct pt_regs *regs)
{
-#ifdef CONFIG_SHOW_REGS
printf("\nSP: " REG_FMT " GP: " REG_FMT " TP: " REG_FMT "\n",
regs->sp, regs->gp, regs->tp);
printf("T0: " REG_FMT " T1: " REG_FMT " T2: " REG_FMT "\n",
@@ -57,7 +56,6 @@
regs->s10, regs->s11, regs->t3);
printf("T4: " REG_FMT " T5: " REG_FMT " T6: " REG_FMT "\n",
regs->t4, regs->t5, regs->t6);
-#endif
}
static void __maybe_unused show_backtrace(struct pt_regs *regs)
@@ -157,7 +155,8 @@
printf("EPC: " REG_FMT " RA: " REG_FMT " reloc adjusted\n",
epc - gd->reloc_off, regs->ra - gd->reloc_off);
- show_regs(regs);
+ if (CONFIG_IS_ENABLED(SHOW_REGS))
+ show_regs(regs);
if (CONFIG_IS_ENABLED(FRAMEPOINTER))
show_backtrace(regs);
show_code(epc);
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c
index 2f29d26..eb88ee7 100644
--- a/board/CZ.NIC/turris_omnia/turris_omnia.c
+++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -23,6 +23,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <fdt_support.h>
#include <hexdump.h>
+#include <i2c_eeprom.h>
#include <time.h>
#include <turris-omnia-mcu-interface.h>
#include <linux/bitops.h>
@@ -46,6 +47,9 @@
#define OMNIA_I2C_EEPROM_CHIP_LEN 2
#define OMNIA_I2C_EEPROM_MAGIC 0x0341a034
+#define OMNIA_RESET_TO_LOWER_DDR_SPEED 9
+#define OMNIA_LOWER_DDR_SPEED "1333H"
+
#define A385_SYS_RSTOUT_MASK MVEBU_REGISTER(0x18260)
#define A385_SYS_RSTOUT_MASK_WD BIT(10)
@@ -205,6 +209,20 @@
return ~bitrev32(crc);
}
+static int omnia_mcu_get_reset(void)
+{
+ u8 reset_status;
+ int ret;
+
+ ret = omnia_mcu_read(CMD_GET_RESET, &reset_status, 1);
+ if (ret) {
+ printf("omnia_mcu_read failed: %i, reset status unknown!\n", ret);
+ return ret;
+ }
+
+ return reset_status;
+}
+
/* Can only be called after relocation, since it needs cleared BSS */
static int omnia_mcu_board_info(char *serial, u8 *mac, char *version)
{
@@ -462,20 +480,27 @@
return true;
}
+static struct udevice *omnia_get_eeprom(void)
+{
+ return omnia_get_i2c_chip("EEPROM", OMNIA_I2C_EEPROM_CHIP_ADDR,
+ OMNIA_I2C_EEPROM_CHIP_LEN);
+}
+
static bool omnia_read_eeprom(struct omnia_eeprom *oep)
{
- struct udevice *chip;
+ struct udevice *eeprom = omnia_get_eeprom();
int ret;
- chip = omnia_get_i2c_chip("EEPROM", OMNIA_I2C_EEPROM_CHIP_ADDR,
- OMNIA_I2C_EEPROM_CHIP_LEN);
-
- if (!chip)
+ if (!eeprom)
return false;
- ret = dm_i2c_read(chip, 0, (void *)oep, sizeof(*oep));
+ if (IS_ENABLED(CONFIG_SPL_BUILD))
+ ret = dm_i2c_read(eeprom, 0, (void *)oep, sizeof(*oep));
+ else
+ ret = i2c_eeprom_read(eeprom, 0, (void *)oep, sizeof(*oep));
+
if (ret) {
- printf("dm_i2c_read failed: %i, cannot read EEPROM\n", ret);
+ printf("cannot read EEPROM: %d\n", ret);
return false;
}
@@ -497,6 +522,35 @@
return true;
}
+static void omnia_eeprom_set_lower_ddr_speed(void)
+{
+ struct udevice *eeprom = omnia_get_eeprom();
+ struct omnia_eeprom oep;
+ int ret;
+
+ if (!eeprom || !omnia_read_eeprom(&oep))
+ return;
+
+ puts("Setting DDR speed to " OMNIA_LOWER_DDR_SPEED " in EEPROM as requested by reset button... ");
+
+ /* check if already set */
+ if (!strncmp(oep.ddr_speed, OMNIA_LOWER_DDR_SPEED, sizeof(oep.ddr_speed)) &&
+ (oep.old_ddr_training == 0 || oep.old_ddr_training == 0xff)) {
+ puts("was already set\n");
+ return;
+ }
+
+ strncpy(oep.ddr_speed, OMNIA_LOWER_DDR_SPEED, sizeof(oep.ddr_speed));
+ oep.old_ddr_training = 0xff;
+ oep.crc2 = crc32(0, (const void *)&oep, offsetof(struct omnia_eeprom, crc2));
+
+ ret = i2c_eeprom_write(eeprom, 0, (const void *)&oep, sizeof(oep));
+ if (ret)
+ printf("cannot write EEPROM: %d\n", ret);
+ else
+ puts("done\n");
+}
+
int omnia_get_ram_size_gb(void)
{
static int ram_size;
@@ -526,6 +580,13 @@
{
struct omnia_eeprom oep;
+ /*
+ * If lower DDR speed is requested by reset button, we can't use old DDR
+ * training algorithm.
+ */
+ if (omnia_mcu_get_reset() == OMNIA_RESET_TO_LOWER_DDR_SPEED)
+ return false;
+
if (!omnia_read_eeprom(&oep))
return false;
@@ -706,13 +767,19 @@
const struct omnia_ddr_speed *setting;
const char *speed;
static bool done;
+ int reset_status;
if (done)
return;
done = true;
- speed = omnia_get_ddr_speed();
+ reset_status = omnia_mcu_get_reset();
+ if (reset_status == OMNIA_RESET_TO_LOWER_DDR_SPEED)
+ speed = OMNIA_LOWER_DDR_SPEED;
+ else
+ speed = omnia_get_ddr_speed();
+
if (!speed)
return;
@@ -729,7 +796,10 @@
if (params->speed_bin_index == setting->speed_bin)
return;
- printf("Fixing up DDR3 speed (EEPROM defines %s)\n", speed);
+ if (reset_status == OMNIA_RESET_TO_LOWER_DDR_SPEED)
+ printf("Fixing up DDR3 speed to %s as requested by reset button\n", speed);
+ else
+ printf("Fixing up DDR3 speed (EEPROM defines %s)\n", speed);
params->speed_bin_index = setting->speed_bin;
params->memory_freq = setting->freq;
@@ -766,8 +836,7 @@
static void handle_reset_button(void)
{
const char * const vars[1] = { "bootcmd_rescue", };
- int ret;
- u8 reset_status;
+ int reset_status;
/*
* Ensure that bootcmd_rescue has always stock value, so that running
@@ -776,12 +845,12 @@
*/
env_set_default_vars(1, (char * const *)vars, 0);
- ret = omnia_mcu_read(CMD_GET_RESET, &reset_status, 1);
- if (ret) {
- printf("omnia_mcu_read failed: %i, reset status unknown!\n",
- ret);
+ reset_status = omnia_mcu_get_reset();
+ if (reset_status < 0)
return;
- }
+
+ if (reset_status == OMNIA_RESET_TO_LOWER_DDR_SPEED)
+ return omnia_eeprom_set_lower_ddr_speed();
env_set_ulong("omnia_reset", reset_status);
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index b794b73..f55c6b5 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -170,23 +170,32 @@
{
const char *compat;
const char *model;
+ int compat_size;
spl_fdt_fixup_mars(fdt);
if (!get_mmc_size_from_eeprom()) {
int offset;
+ static const char
+ compat_cm_lite[] = "milkv,mars-cm-lite\0starfive,jh7110";
model = "Milk-V Mars CM Lite";
- compat = "milkv,mars-cm-lite\0starfive,jh7110";
+ compat = compat_cm_lite;
+ compat_size = sizeof(compat_cm_lite);
offset = fdt_path_offset(fdt, "/soc/pinctrl/mmc0-pins/mmc0-pins-rest");
/* GPIOMUX(22, GPOUT_SYS_SDIO0_RST, GPOEN_ENABLE, GPI_NONE) */
fdt_setprop_u32(fdt, offset, "pinmux", 0xff130016);
} else {
+ static const char
+ compat_cm[] = "milkv,mars-cm\0starfive,jh7110";
+
model = "Milk-V Mars CM";
- compat = "milkv,mars-cm\0starfive,jh7110";
+ compat = compat_cm;
+ compat_size = sizeof(compat_cm);
}
- fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat));
+ fdt_setprop(fdt, fdt_path_offset(fdt, "/"),
+ "compatible", compat, compat_size);
fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", model);
}
diff --git a/cmd/riscv/exception.c b/cmd/riscv/exception.c
index 2b58b1c..16e3353 100644
--- a/cmd/riscv/exception.c
+++ b/cmd/riscv/exception.c
@@ -36,6 +36,14 @@
return CMD_RET_SUCCESS;
}
+static int do_rdcycle(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ printf("cycle = 0x%lx\n", csr_read(CSR_CYCLE));
+
+ return CMD_RET_SUCCESS;
+}
+
static int do_unaligned(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
@@ -62,6 +70,8 @@
"", ""),
U_BOOT_CMD_MKENT(ialign16, CONFIG_SYS_MAXARGS, 1, do_ialign16,
"", ""),
+ U_BOOT_CMD_MKENT(rdcycle, CONFIG_SYS_MAXARGS, 1, do_rdcycle,
+ "", ""),
U_BOOT_CMD_MKENT(unaligned, CONFIG_SYS_MAXARGS, 1, do_unaligned,
"", ""),
U_BOOT_CMD_MKENT(undefined, CONFIG_SYS_MAXARGS, 1, do_undefined,
@@ -74,7 +84,8 @@
" compressed - compressed instruction\n"
" ebreak - breakpoint\n"
" ialign16 - 16 bit aligned instruction\n"
- " undefined - illegal instruction\n"
- " unaligned - load address misaligned\n");
+ " rdcycle - read cycle CSR\n"
+ " unaligned - load address misaligned\n"
+ " undefined - illegal instruction\n");
#include <exception.h>
diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig
index c8756a3..93f0bc5 100644
--- a/configs/turris_omnia_defconfig
+++ b/configs/turris_omnia_defconfig
@@ -92,7 +92,6 @@
CONFIG_AHCI_PCI=y
CONFIG_AHCI_MVEBU=y
CONFIG_DM_PCA953X=y
-CONFIG_I2C_EEPROM=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_DM_MTD=y
diff --git a/drivers/clk/analogbits/wrpll-cln28hpc.c b/drivers/clk/analogbits/wrpll-cln28hpc.c
index a3cb109..537c696 100644
--- a/drivers/clk/analogbits/wrpll-cln28hpc.c
+++ b/drivers/clk/analogbits/wrpll-cln28hpc.c
@@ -81,7 +81,7 @@
{
if (post_divr_freq < MIN_POST_DIVR_FREQ ||
post_divr_freq > MAX_POST_DIVR_FREQ) {
- WARN(1, "%s: post-divider reference freq out of range: %lu",
+ WARN(1, "%s: post-divider reference freq out of range: %lu\n",
__func__, post_divr_freq);
return -ERANGE;
}
@@ -229,7 +229,7 @@
int range;
if (c->flags == 0) {
- WARN(1, "%s called with uninitialized PLL config", __func__);
+ WARN(1, "%s called with uninitialized PLL config\n", __func__);
return -EINVAL;
}
@@ -335,7 +335,7 @@
u64 n;
if (c->flags & WRPLL_FLAGS_EXT_FEEDBACK_MASK) {
- WARN(1, "external feedback mode not yet supported");
+ WARN(1, "external feedback mode not yet supported\n");
return ULONG_MAX;
}
diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index ceb2c6f..e55a26a 100644
--- a/drivers/clk/sifive/fu540-prci.c
+++ b/drivers/clk/sifive/fu540-prci.c
@@ -58,7 +58,7 @@
};
/* List of clock controls provided by the PRCI */
-struct __prci_clock __prci_init_clocks_fu540[] = {
+static struct __prci_clock __prci_init_clocks_fu540[] = {
[PRCI_CLK_COREPLL] = {
.name = "corepll",
.parent_name = "hfclk",
@@ -83,3 +83,8 @@
.ops = &sifive_fu540_prci_tlclksel_clk_ops,
},
};
+
+const struct prci_clk_desc prci_clk_fu540 = {
+ .clks = __prci_init_clocks_fu540,
+ .num_clks = ARRAY_SIZE(__prci_init_clocks_fu540),
+};
diff --git a/drivers/clk/sifive/fu540-prci.h b/drivers/clk/sifive/fu540-prci.h
deleted file mode 100644
index 1133011..0000000
--- a/drivers/clk/sifive/fu540-prci.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2020-2021 SiFive, Inc.
- * Zong Li
- * Pragnesh Patel
- */
-
-#ifndef __SIFIVE_CLK_FU540_PRCI_H
-#define __SIFIVE_CLK_FU540_PRCI_H
-
-#include "sifive-prci.h"
-
-#define NUM_CLOCK_FU540 4
-
-extern struct __prci_clock __prci_init_clocks_fu540[NUM_CLOCK_FU540];
-
-static const struct prci_clk_desc prci_clk_fu540 = {
- .clks = __prci_init_clocks_fu540,
- .num_clks = ARRAY_SIZE(__prci_init_clocks_fu540),
-};
-
-#endif /* __SIFIVE_CLK_FU540_PRCI_H */
diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c
index 5edc864..4274b21 100644
--- a/drivers/clk/sifive/fu740-prci.c
+++ b/drivers/clk/sifive/fu740-prci.c
@@ -102,7 +102,7 @@
};
/* List of clock controls provided by the PRCI */
-struct __prci_clock __prci_init_clocks_fu740[] = {
+static struct __prci_clock __prci_init_clocks_fu740[] = {
[FU740_PRCI_CLK_COREPLL] = {
.name = "corepll",
.parent_name = "hfclk",
@@ -156,3 +156,8 @@
.pwd = &__prci_pcieaux_data,
}
};
+
+const struct prci_clk_desc prci_clk_fu740 = {
+ .clks = __prci_init_clocks_fu740,
+ .num_clks = ARRAY_SIZE(__prci_init_clocks_fu740),
+};
diff --git a/drivers/clk/sifive/fu740-prci.h b/drivers/clk/sifive/fu740-prci.h
deleted file mode 100644
index b74f078..0000000
--- a/drivers/clk/sifive/fu740-prci.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2020-2021 SiFive, Inc.
- * Zong Li
- * Pragnesh Patel
- */
-
-#ifndef __SIFIVE_CLK_FU740_PRCI_H
-#define __SIFIVE_CLK_FU740_PRCI_H
-
-#include "sifive-prci.h"
-
-#define NUM_CLOCK_FU740 9
-
-extern struct __prci_clock __prci_init_clocks_fu740[NUM_CLOCK_FU740];
-
-static const struct prci_clk_desc prci_clk_fu740 = {
- .clks = __prci_init_clocks_fu740,
- .num_clks = ARRAY_SIZE(__prci_init_clocks_fu740),
-};
-
-#endif /* __SIFIVE_CLK_FU740_PRCI_H */
diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c
index 5ea8606..aa26d3a 100644
--- a/drivers/clk/sifive/sifive-prci.c
+++ b/drivers/clk/sifive/sifive-prci.c
@@ -33,8 +33,7 @@
#include <linux/math64.h>
#include <dt-bindings/clock/sifive-fu740-prci.h>
-#include "fu540-prci.h"
-#include "fu740-prci.h"
+#include "sifive-prci.h"
/*
* Private functions
diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h
index 5ce33d6..b391698 100644
--- a/drivers/clk/sifive/sifive-prci.h
+++ b/drivers/clk/sifive/sifive-prci.h
@@ -320,4 +320,8 @@
int sifive_prci_clock_enable(struct __prci_clock *pc, bool enable);
+/* Clock driver data */
+extern const struct prci_clk_desc prci_clk_fu540;
+extern const struct prci_clk_desc prci_clk_fu740;
+
#endif /* __SIFIVE_CLK_SIFIVE_PRCI_H */
diff --git a/drivers/mtd/renesas_rpc_hf.c b/drivers/mtd/renesas_rpc_hf.c
index 941f204..0354582 100644
--- a/drivers/mtd/renesas_rpc_hf.c
+++ b/drivers/mtd/renesas_rpc_hf.c
@@ -387,6 +387,7 @@
static const struct udevice_id rpc_hf_ids[] = {
{ .compatible = "renesas,r7s72100-rpc-if" },
{ .compatible = "renesas,rcar-gen3-rpc-if" },
+ { .compatible = "renesas,rcar-gen4-rpc-if" },
{}
};
diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c
index e6b602c..f1e6f9f 100644
--- a/drivers/spi/renesas_rpc_spi.c
+++ b/drivers/spi/renesas_rpc_spi.c
@@ -145,6 +145,12 @@
#define RPC_PHYCNT_WBUF BIT(2)
#define RPC_PHYCNT_MEM(v) (((v) & 0x3) << 0)
+#define RPCIF_PHYOFFSET1 0x0080 /* R/W */
+#define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28)
+
+#define RPCIF_PHYOFFSET2 0x0084 /* R/W */
+#define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8)
+
#define RPC_PHYINT 0x0088 /* R/W */
#define RPC_PHYINT_RSTEN BIT(18)
#define RPC_PHYINT_WPEN BIT(17)
@@ -227,6 +233,12 @@
struct udevice *bus = dev->parent;
struct rpc_spi_priv *priv = dev_get_priv(bus);
+ setbits_le32(priv->regs + RPCIF_PHYOFFSET1,
+ RPCIF_PHYOFFSET1_DDRTMG(3));
+ clrsetbits_le32(priv->regs + RPCIF_PHYOFFSET2,
+ RPCIF_PHYOFFSET2_OCTTMG(7),
+ RPCIF_PHYOFFSET2_OCTTMG(4));
+
/* NOTE: The 0x260 are undocumented bits, but they must be set. */
writel(RPC_PHYCNT_CAL | rpc_spi_get_strobe_delay() | 0x260,
priv->regs + RPC_PHYCNT);
@@ -277,24 +289,24 @@
writel(RPC_DRCMR_CMD(op->cmd.opcode), priv->regs + RPC_DRCMR);
smenr |= RPC_DRENR_CDE;
- writel(0, priv->regs + RPC_DREAR);
if (op->addr.nbytes == 4) {
writel(RPC_DREAR_EAV(offset >> 25) | RPC_DREAR_EAC(1),
priv->regs + RPC_DREAR);
smenr |= RPC_DRENR_ADE(0xF);
} else if (op->addr.nbytes == 3) {
+ writel(0, priv->regs + RPC_DREAR);
smenr |= RPC_DRENR_ADE(0x7);
} else {
+ writel(0, priv->regs + RPC_DREAR);
smenr |= RPC_DRENR_ADE(0);
}
- writel(0, priv->regs + RPC_DRDMCR);
- if (op->dummy.nbytes) {
- writel(8 * op->dummy.nbytes - 1, priv->regs + RPC_DRDMCR);
+ if (op->dummy.nbytes)
smenr |= RPC_DRENR_DME;
- }
+ writel(8 * op->dummy.nbytes - 1, priv->regs + RPC_DRDMCR);
writel(0, priv->regs + RPC_DROPR);
+ writel(0, priv->regs + RPC_DRDRENR);
writel(smenr, priv->regs + RPC_DRENR);
memcpy_fromio(din, (void *)(priv->extr + offset), op->data.nbytes);
@@ -453,6 +465,7 @@
static const struct udevice_id rpc_spi_ids[] = {
{ .compatible = "renesas,r7s72100-rpc-if" },
{ .compatible = "renesas,rcar-gen3-rpc-if" },
+ { .compatible = "renesas,rcar-gen4-rpc-if" },
{ }
};