commit cb6d04d60664210d2e198192e164b6cfc8bade83
author Chao Fu <B44548@freescale.com> Tue May 06 09:13:03 2014 +0800
committer Albert ARIBAUD <albert.u.boot@aribaud.net> Mon Jun 09 09:18:15 2014 +0200
tree e8b099002c921a2304bcf31d12210e2f90217c9a
parent 9d2ca0984bda37bb58bf7f58f1626450e28a6595

arm: vf610: Add QSPI support for VF610TWR

Add QSPI support for VF610TWR, such as clock and iomux.

Signed-off-by: Alison Wang <Huan.Wang@freescale.com>
Signed-off-by: Chao Fu <b44548@freescale.com>

arch/arm/include/asm/arch-vf610/imx-regs.h

diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index 0c28e1b..bd6f680 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -87,6 +87,8 @@
 #define ENET_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00050000)
 #define ENET1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00051000)
 
+#define QSPI0_AMBA_BASE		0x20000000
+
 /* MUX mode and PAD ctrl are in one register */
 #define CONFIG_IOMUX_SHARE_CONF_REG