| commit | bd6363a7b77f0a5737b736f80179b6f53ef2cf7c | [log] [tgz] |
|---|---|---|
| author | Marek Vasut <marex@denx.de> | Tue May 08 18:44:43 2018 +0200 |
| committer | Marek Vasut <marex@denx.de> | Sat Mar 09 17:59:14 2019 +0100 |
| tree | 1da56b2c374dbf3a72806923ffcd040b510ca95b | |
| parent | 60082d3b3ff17fc0c5ae6c1cdd176219554ed61f [diff] |
ARM: socfpga: Fix Arria10 SPI and NAND U-Boot offset The SPL size on Gen5 is 4*64kiB, but on A10 it is 4*256kiB. Handle the difference. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>