diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts
index e720ff1..2c7fa79 100644
--- a/arch/arm/dts/stm32f746-disco.dts
+++ b/arch/arm/dts/stm32f746-disco.dts
@@ -94,6 +94,96 @@
 	clock-frequency = <25000000>;
 };
 
+&pinctrl {
+	usart1_pins_a: usart1@0	{
+		pins1 {
+		       pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
+				bias-disable;
+				drive-push-pull;
+				slew-rate = <2>;
+		};
+		pins2 {
+			pinmux = <STM32F746_PB7_FUNC_USART1_RX>;
+			bias-disable;
+		};
+	};
+
+	ethernet_mii: mii@0 {
+	      pins {
+		      pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
+			     <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
+			     <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
+			     <STM32F746_PA2_FUNC_ETH_MDIO>,
+			     <STM32F746_PC1_FUNC_ETH_MDC>,
+			     <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
+			     <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
+			     <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
+			     <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
+		      slew-rate = <2>;
+	      };
+	};
+
+	qspi_pins: qspi@0 {
+		pins {
+			pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
+			       <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
+			       <STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>,
+			       <STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>,
+			       <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>,
+			       <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>;
+			slew-rate = <2>;
+		};
+	};
+
+	fmc_pins: fmc@0 {
+		pins {
+			pinmux = <STM32F746_PD10_FUNC_FMC_D15>,
+				 <STM32F746_PD9_FUNC_FMC_D14>,
+				 <STM32F746_PD8_FUNC_FMC_D13>,
+				 <STM32F746_PE15_FUNC_FMC_D12>,
+				 <STM32F746_PE14_FUNC_FMC_D11>,
+				 <STM32F746_PE13_FUNC_FMC_D10>,
+				 <STM32F746_PE12_FUNC_FMC_D9>,
+				 <STM32F746_PE11_FUNC_FMC_D8>,
+				 <STM32F746_PE10_FUNC_FMC_D7>,
+				 <STM32F746_PE9_FUNC_FMC_D6>,
+				 <STM32F746_PE8_FUNC_FMC_D5>,
+				 <STM32F746_PE7_FUNC_FMC_D4>,
+				 <STM32F746_PD1_FUNC_FMC_D3>,
+				 <STM32F746_PD0_FUNC_FMC_D2>,
+				 <STM32F746_PD15_FUNC_FMC_D1>,
+				 <STM32F746_PD14_FUNC_FMC_D0>,
+
+				 <STM32F746_PE1_FUNC_FMC_NBL1>,
+				 <STM32F746_PE0_FUNC_FMC_NBL0>,
+
+				 <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>,
+				 <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>,
+
+				 <STM32F746_PG1_FUNC_FMC_A11>,
+				 <STM32F746_PG0_FUNC_FMC_A10>,
+				 <STM32F746_PF15_FUNC_FMC_A9>,
+				 <STM32F746_PF14_FUNC_FMC_A8>,
+				 <STM32F746_PF13_FUNC_FMC_A7>,
+				 <STM32F746_PF12_FUNC_FMC_A6>,
+				 <STM32F746_PF5_FUNC_FMC_A5>,
+				 <STM32F746_PF4_FUNC_FMC_A4>,
+				 <STM32F746_PF3_FUNC_FMC_A3>,
+				 <STM32F746_PF2_FUNC_FMC_A2>,
+				 <STM32F746_PF1_FUNC_FMC_A1>,
+				 <STM32F746_PF0_FUNC_FMC_A0>,
+
+				 <STM32F746_PH3_FUNC_FMC_SDNE0>,
+				 <STM32F746_PH5_FUNC_FMC_SDNWE>,
+				 <STM32F746_PF11_FUNC_FMC_SDNRAS>,
+				 <STM32F746_PG15_FUNC_FMC_SDNCAS>,
+				 <STM32F746_PC3_FUNC_FMC_SDCKE0>,
+				 <STM32F746_PG8_FUNC_FMC_SDCLK>;
+			  slew-rate = <2>;
+		};
+	};
+};
+
 &usart1 {
 	pinctrl-0 = <&usart1_pins_a>;
 	pinctrl-names = "default";
diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index 865d5cf..ac24d98 100644
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -225,92 +225,6 @@
 				u-boot,dm-pre-reloc;
 			};
 
-			usart1_pins_a: usart1@0 {
-				pins1 {
-					pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
-					bias-disable;
-					drive-push-pull;
-					slew-rate = <2>;
-				};
-				pins2 {
-					pinmux = <STM32F746_PB7_FUNC_USART1_RX>;
-					bias-disable;
-				};
-			};
-			ethernet_mii: mii@0 {
-				pins {
-					pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
-						 <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
-						 <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
-						 <STM32F746_PA2_FUNC_ETH_MDIO>,
-						 <STM32F746_PC1_FUNC_ETH_MDC>,
-						 <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
-						 <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
-						 <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
-						 <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
-					slew-rate = <2>;
-				};
-			};
-			qspi_pins: qspi@0{
-				pins {
-					pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
-						 <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
-						 <STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>,
-						 <STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>,
-						 <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>,
-						 <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>;
-					slew-rate = <2>;
-				};
-			};
-
-			fmc_pins: fmc@0 {
-				pins {
-					pinmux = <STM32F746_PD10_FUNC_FMC_D15>,
-						 <STM32F746_PD9_FUNC_FMC_D14>,
-						 <STM32F746_PD8_FUNC_FMC_D13>,
-						 <STM32F746_PE15_FUNC_FMC_D12>,
-						 <STM32F746_PE14_FUNC_FMC_D11>,
-						 <STM32F746_PE13_FUNC_FMC_D10>,
-						 <STM32F746_PE12_FUNC_FMC_D9>,
-						 <STM32F746_PE11_FUNC_FMC_D8>,
-						 <STM32F746_PE10_FUNC_FMC_D7>,
-						 <STM32F746_PE9_FUNC_FMC_D6>,
-						 <STM32F746_PE8_FUNC_FMC_D5>,
-						 <STM32F746_PE7_FUNC_FMC_D4>,
-						 <STM32F746_PD1_FUNC_FMC_D3>,
-						 <STM32F746_PD0_FUNC_FMC_D2>,
-						 <STM32F746_PD15_FUNC_FMC_D1>,
-						 <STM32F746_PD14_FUNC_FMC_D0>,
-
-						 <STM32F746_PE1_FUNC_FMC_NBL1>,
-						 <STM32F746_PE0_FUNC_FMC_NBL0>,
-
-						 <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>,
-						 <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>,
-
-						 <STM32F746_PG1_FUNC_FMC_A11>,
-						 <STM32F746_PG0_FUNC_FMC_A10>,
-						 <STM32F746_PF15_FUNC_FMC_A9>,
-						 <STM32F746_PF14_FUNC_FMC_A8>,
-						 <STM32F746_PF13_FUNC_FMC_A7>,
-						 <STM32F746_PF12_FUNC_FMC_A6>,
-						 <STM32F746_PF5_FUNC_FMC_A5>,
-						 <STM32F746_PF4_FUNC_FMC_A4>,
-						 <STM32F746_PF3_FUNC_FMC_A3>,
-						 <STM32F746_PF2_FUNC_FMC_A2>,
-						 <STM32F746_PF1_FUNC_FMC_A1>,
-						 <STM32F746_PF0_FUNC_FMC_A0>,
-
-						 <STM32F746_PH3_FUNC_FMC_SDNE0>,
-						 <STM32F746_PH5_FUNC_FMC_SDNWE>,
-						 <STM32F746_PF11_FUNC_FMC_SDNRAS>,
-						 <STM32F746_PG15_FUNC_FMC_SDNCAS>,
-						 <STM32F746_PC3_FUNC_FMC_SDCKE0>,
-						 <STM32F746_PG8_FUNC_FMC_SDCLK>;
-					slew-rate = <2>;
-				};
-			};
-
 		};
 	};
 };