diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/event.c b/board/MAI/bios_emulator/scitech/src/pm/win32/event.c
index 86448e3..6388052 100644
--- a/board/MAI/bios_emulator/scitech/src/pm/win32/event.c
+++ b/board/MAI/bios_emulator/scitech/src/pm/win32/event.c
@@ -147,14 +147,14 @@
 		if (EVT.oldMove != -1) {
 		    EVT.evtq[EVT.oldMove].where_x = evt.where_x;/* Modify existing one  */
 		    EVT.evtq[EVT.oldMove].where_y = evt.where_y;
-/*                  EVT.evtq[EVT.oldMove].relative_x += mickeyX;    // TODO! */
-/*                  EVT.evtq[EVT.oldMove].relative_y += mickeyY;    // TODO! */
+/*                  EVT.evtq[EVT.oldMove].relative_x += mickeyX;    / / TODO! */
+/*                  EVT.evtq[EVT.oldMove].relative_y += mickeyY;    / / TODO! */
 		    evt.what = 0;
 		    }
 		else {
 		    EVT.oldMove = EVT.freeHead; /* Save id of this move event   */
-/*                  evt.relative_x = mickeyX;    // TODO! */
-/*                  evt.relative_y = mickeyY;    // TODO! */
+/*                  evt.relative_x = mickeyX;    / / TODO! */
+/*                  evt.relative_y = mickeyY;    / / TODO! */
 		    }
 		}
 	    else
diff --git a/board/netstar/crcek.S b/board/netstar/crcek.S
index 8726cc9..a74abf9 100644
--- a/board/netstar/crcek.S
+++ b/board/netstar/crcek.S
@@ -113,7 +113,7 @@
 	ldr	r0, MPU_CLKM_BASE		@ base of CLOCK unit
 	mov	r1, #(1 << 10)			@ disable idle mode do not check
 						@ nWAKEUP pin, other remain active
-	strh	r1, [r0, #0x04] 
+	strh	r1, [r0, #0x04]
 	ldr	r1, EN_CLK_VAL
 	strh	r1, [r0, #0x08]
 	mov	r1, #0x003f			@ FLASH.RP not enabled in idle and
diff --git a/board/netstar/eeprom.c b/board/netstar/eeprom.c
index c7ff79b..fef3822 100644
--- a/board/netstar/eeprom.c
+++ b/board/netstar/eeprom.c
@@ -213,4 +213,3 @@
 
 	return 0;
 }
-
diff --git a/board/netstar/nand.c b/board/netstar/nand.c
index 4ce6ca1..f470c1a 100644
--- a/board/netstar/nand.c
+++ b/board/netstar/nand.c
@@ -57,11 +57,10 @@
 
 void board_nand_init(struct nand_chip *nand)
 {
-        nand->options = NAND_SAMSUNG_LP_OPTIONS;
+	nand->options = NAND_SAMSUNG_LP_OPTIONS;
 	nand->eccmode = NAND_ECC_SOFT;
-        nand->hwcontrol = netstar_nand_hwcontrol;
+	nand->hwcontrol = netstar_nand_hwcontrol;
 /*	nand->dev_ready = netstar_nand_ready; */
 	nand->chip_delay = 18;
 }
 #endif
-
diff --git a/board/netstar/netstar.c b/board/netstar/netstar.c
index 331e092..d6b620c 100644
--- a/board/netstar/netstar.c
+++ b/board/netstar/netstar.c
@@ -59,4 +59,3 @@
 {
 	return 0;
 }
-
diff --git a/board/netstar/setup.S b/board/netstar/setup.S
index 68747c9..5dacc9c 100644
--- a/board/netstar/setup.S
+++ b/board/netstar/setup.S
@@ -58,10 +58,10 @@
 VAL_EMIFF_SDRAM_CONFIG:		.word ((0 << 0) | (0 << 1) | (3 << 2) | (0xd << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27))
 #endif
 
-VAL_EMIFF_SDRAM_CONFIG2:	.word 0x00000003 
+VAL_EMIFF_SDRAM_CONFIG2:	.word 0x00000003
 VAL_EMIFF_MRS:			.word 0x00000037
 
-/* 
+/*
  * GPIO04 - Green LED (Red LED is connected to LED Pulse Generator)
  * GPIO07 - LAN91C111 reset
  */
@@ -106,7 +106,7 @@
 	.align 1
 	.byte 0x00		@ FUNC_MUX_CTRL_0
 	.byte 0x04		@ FUNC_MUX_CTRL_1
-	.byte 0x08		@ FUNC_MUX_CTRL_2 
+	.byte 0x08		@ FUNC_MUX_CTRL_2
 	.byte 0x10		@ FUNC_MUX_CTRL_3
 	.byte 0x14		@ FUNC_MUX_CTRL_4
 	.byte 0x18		@ FUNC_MUX_CTRL_5
@@ -180,7 +180,7 @@
 	ldr	r0, OMAP5910_MPU_CLKM_BASE	@ base of CLOCK unit
 	mov	r1, #(1 << 10)			@ disable idle mode do not check
 						@ nWAKEUP pin, other remain active
-	strh	r1, [r0, #0x04] 
+	strh	r1, [r0, #0x04]
 	ldr	r1, _OMAP5910_ARM_EN_CLK
 	strh	r1, [r0, #0x08]
 	mov	r1, #0x003f			@ FLASH.RP not enabled in idle and
@@ -190,7 +190,7 @@
 	ldr     r0, MUX_CONFIG_BASE
 	adr	r1, MUX_CONFIG_VALUES
 	adr	r2, MUX_CONFIG_OFFSETS
-next_mux_cfg:	 
+next_mux_cfg:
 	ldrb	r3, [r2], #1
 	ldr	r4, [r1], #4
 	cmp	r3, #0xff
@@ -237,15 +237,15 @@
 	strh	r1, [r0, #0x34]
 
 	/* Setup clock divisors */
-	ldr	r0, OMAP5910_ULPD_PWR_MNG_BASE	@ base of ULDPL DPLL1 register    
+	ldr	r0, OMAP5910_ULPD_PWR_MNG_BASE	@ base of ULDPL DPLL1 register
 
 	mov	r1, #0x0010			@ set PLL_ENABLE
-	orr	r1, r1, #0x2000			@ set IOB to new locking 
-	strh	r1, [r0]			@ write 
+	orr	r1, r1, #0x2000			@ set IOB to new locking
+	strh	r1, [r0]			@ write
 
 ulocking:
 	ldrh	r1, [r0]			@ get DPLL value
-	tst	r1, #1			      
+	tst	r1, #1
 	beq	ulocking			@ while LOCK not set
 
 	/* EMIF init */
@@ -254,7 +254,7 @@
 	bic	r1, r1, #0x0c			@ pwr down disabled, flash WP
 	orr	r1, r1, #0x01
 	str	r1, [r0, #0x0c]
-	
+
 	ldr	r1, VAL_EMIFS_CS0_CONFIG
 	str	r1, [r0, #0x10]			@ EMIFS_CS0_CONFIG
 	ldr	r1, VAL_EMIFS_CS1_CONFIG
diff --git a/board/ppmc7xx/config.mk b/board/ppmc7xx/config.mk
index d8eac77..b5b46dc 100644
--- a/board/ppmc7xx/config.mk
+++ b/board/ppmc7xx/config.mk
@@ -22,7 +22,6 @@
 # along with this program; if not, write to the Free Software
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
-#
 
 TEXT_BASE = 0xFFF00000
 TEXT_END  = 0xFFF40000
diff --git a/board/sbc2410x/lowlevel_init.S b/board/sbc2410x/lowlevel_init.S
index 5bfa14a..3df63cd 100644
--- a/board/sbc2410x/lowlevel_init.S
+++ b/board/sbc2410x/lowlevel_init.S
@@ -43,82 +43,82 @@
 #define BWSCON	0x48000000
 
 /* BWSCON */
-#define DW8		 	(0x0)
-#define DW16		 	(0x1)
-#define DW32		 	(0x2)
-#define WAIT		 	(0x1<<2)
-#define UBLB		 	(0x1<<3)
+#define DW8			(0x0)
+#define DW16			(0x1)
+#define DW32			(0x2)
+#define WAIT			(0x1<<2)
+#define UBLB			(0x1<<3)
 
-#define B1_BWSCON	  	(DW16)
-#define B2_BWSCON	  	(DW16)
-#define B3_BWSCON	  	(DW16 + WAIT + UBLB)
-#define B4_BWSCON	  	(DW16)
-#define B5_BWSCON	  	(DW16)
-#define B6_BWSCON	  	(DW32)
-#define B7_BWSCON	  	(DW32)
+#define B1_BWSCON		(DW16)
+#define B2_BWSCON		(DW16)
+#define B3_BWSCON		(DW16 + WAIT + UBLB)
+#define B4_BWSCON		(DW16)
+#define B5_BWSCON		(DW16)
+#define B6_BWSCON		(DW32)
+#define B7_BWSCON		(DW32)
 
-#define B0_Tacs		 	0x0	
-#define B0_Tcos		 	0x0	
-#define B0_Tacc		 	0x7	
-#define B0_Tcoh		 	0x0	
-#define B0_Tah		 	0x0
-#define B0_Tacp		 	0x0
-#define B0_PMC		 	0x0	
+#define B0_Tacs			0x0
+#define B0_Tcos			0x0
+#define B0_Tacc			0x7
+#define B0_Tcoh			0x0
+#define B0_Tah			0x0
+#define B0_Tacp			0x0
+#define B0_PMC			0x0
 
-#define B1_Tacs		 	0x0	
-#define B1_Tcos		 	0x0	
-#define B1_Tacc		 	0x7	
-#define B1_Tcoh		 	0x0	
-#define B1_Tah		 	0x0	
-#define B1_Tacp		 	0x0
-#define B1_PMC		 	0x0	
+#define B1_Tacs			0x0
+#define B1_Tcos			0x0
+#define B1_Tacc			0x7
+#define B1_Tcoh			0x0
+#define B1_Tah			0x0
+#define B1_Tacp			0x0
+#define B1_PMC			0x0
 
-#define B2_Tacs		 	0x0
-#define B2_Tcos		 	0x0
-#define B2_Tacc		 	0x7
-#define B2_Tcoh		 	0x0
-#define B2_Tah		 	0x0
-#define B2_Tacp		 	0x0
-#define B2_PMC		 	0x0
+#define B2_Tacs			0x0
+#define B2_Tcos			0x0
+#define B2_Tacc			0x7
+#define B2_Tcoh			0x0
+#define B2_Tah			0x0
+#define B2_Tacp			0x0
+#define B2_PMC			0x0
 
-#define B3_Tacs		 	0xc
-#define B3_Tcos		 	0x7
-#define B3_Tacc		 	0xf
-#define B3_Tcoh		 	0x1
-#define B3_Tah		 	0x0
-#define B3_Tacp		 	0x0
-#define B3_PMC		 	0x0
+#define B3_Tacs			0xc
+#define B3_Tcos			0x7
+#define B3_Tacc			0xf
+#define B3_Tcoh			0x1
+#define B3_Tah			0x0
+#define B3_Tacp			0x0
+#define B3_PMC			0x0
 
-#define B4_Tacs		 	0x0
-#define B4_Tcos		 	0x0
-#define B4_Tacc		 	0x7
-#define B4_Tcoh		 	0x0
-#define B4_Tah		 	0x0
-#define B4_Tacp		 	0x0
-#define B4_PMC		 	0x0
+#define B4_Tacs			0x0
+#define B4_Tcos			0x0
+#define B4_Tacc			0x7
+#define B4_Tcoh			0x0
+#define B4_Tah			0x0
+#define B4_Tacp			0x0
+#define B4_PMC			0x0
 
-#define B5_Tacs		 	0xc
-#define B5_Tcos		 	0x7
-#define B5_Tacc		 	0xf
-#define B5_Tcoh		 	0x1
-#define B5_Tah		 	0x0
-#define B5_Tacp		 	0x0
-#define B5_PMC		 	0x0
+#define B5_Tacs			0xc
+#define B5_Tcos			0x7
+#define B5_Tacc			0xf
+#define B5_Tcoh			0x1
+#define B5_Tah			0x0
+#define B5_Tacp			0x0
+#define B5_PMC			0x0
 
-#define B6_MT		 	0x3	/* SDRAM */
-#define B6_Trcd	 	 	0x1
-#define B6_SCAN		 	0x1	/* 9bit */
+#define B6_MT			0x3	/* SDRAM */
+#define B6_Trcd			0x1
+#define B6_SCAN			0x1	/* 9bit */
 
-#define B7_MT		 	0x3	/* SDRAM */
-#define B7_Trcd		 	0x1	/* 3clk */
-#define B7_SCAN		 	0x1	/* 9bit */
+#define B7_MT			0x3	/* SDRAM */
+#define B7_Trcd			0x1	/* 3clk */
+#define B7_SCAN			0x1	/* 9bit */
 
 /* REFRESH parameter */
-#define REFEN		 	0x1	/* Refresh enable */
-#define TREFMD		 	0x0	/* CBR(CAS before RAS)/Auto refresh */
-#define Trp		 	0x0	/* 2clk */
-#define Trc		 	0x3	/* 7clk */
-#define Tchr		 	0x2	/* 3clk */
+#define REFEN			0x1	/* Refresh enable */
+#define TREFMD			0x0	/* CBR(CAS before RAS)/Auto refresh */
+#define Trp			0x0	/* 2clk */
+#define Trc			0x3	/* 7clk */
+#define Tchr			0x2	/* 3clk */
 #define REFCNT			0x0459
 /**************************************/