diff --git a/board/netstar/crcek.S b/board/netstar/crcek.S
index 8726cc9..a74abf9 100644
--- a/board/netstar/crcek.S
+++ b/board/netstar/crcek.S
@@ -113,7 +113,7 @@
 	ldr	r0, MPU_CLKM_BASE		@ base of CLOCK unit
 	mov	r1, #(1 << 10)			@ disable idle mode do not check
 						@ nWAKEUP pin, other remain active
-	strh	r1, [r0, #0x04] 
+	strh	r1, [r0, #0x04]
 	ldr	r1, EN_CLK_VAL
 	strh	r1, [r0, #0x08]
 	mov	r1, #0x003f			@ FLASH.RP not enabled in idle and
diff --git a/board/netstar/eeprom.c b/board/netstar/eeprom.c
index c7ff79b..fef3822 100644
--- a/board/netstar/eeprom.c
+++ b/board/netstar/eeprom.c
@@ -213,4 +213,3 @@
 
 	return 0;
 }
-
diff --git a/board/netstar/nand.c b/board/netstar/nand.c
index 4ce6ca1..f470c1a 100644
--- a/board/netstar/nand.c
+++ b/board/netstar/nand.c
@@ -57,11 +57,10 @@
 
 void board_nand_init(struct nand_chip *nand)
 {
-        nand->options = NAND_SAMSUNG_LP_OPTIONS;
+	nand->options = NAND_SAMSUNG_LP_OPTIONS;
 	nand->eccmode = NAND_ECC_SOFT;
-        nand->hwcontrol = netstar_nand_hwcontrol;
+	nand->hwcontrol = netstar_nand_hwcontrol;
 /*	nand->dev_ready = netstar_nand_ready; */
 	nand->chip_delay = 18;
 }
 #endif
-
diff --git a/board/netstar/netstar.c b/board/netstar/netstar.c
index 331e092..d6b620c 100644
--- a/board/netstar/netstar.c
+++ b/board/netstar/netstar.c
@@ -59,4 +59,3 @@
 {
 	return 0;
 }
-
diff --git a/board/netstar/setup.S b/board/netstar/setup.S
index 68747c9..5dacc9c 100644
--- a/board/netstar/setup.S
+++ b/board/netstar/setup.S
@@ -58,10 +58,10 @@
 VAL_EMIFF_SDRAM_CONFIG:		.word ((0 << 0) | (0 << 1) | (3 << 2) | (0xd << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27))
 #endif
 
-VAL_EMIFF_SDRAM_CONFIG2:	.word 0x00000003 
+VAL_EMIFF_SDRAM_CONFIG2:	.word 0x00000003
 VAL_EMIFF_MRS:			.word 0x00000037
 
-/* 
+/*
  * GPIO04 - Green LED (Red LED is connected to LED Pulse Generator)
  * GPIO07 - LAN91C111 reset
  */
@@ -106,7 +106,7 @@
 	.align 1
 	.byte 0x00		@ FUNC_MUX_CTRL_0
 	.byte 0x04		@ FUNC_MUX_CTRL_1
-	.byte 0x08		@ FUNC_MUX_CTRL_2 
+	.byte 0x08		@ FUNC_MUX_CTRL_2
 	.byte 0x10		@ FUNC_MUX_CTRL_3
 	.byte 0x14		@ FUNC_MUX_CTRL_4
 	.byte 0x18		@ FUNC_MUX_CTRL_5
@@ -180,7 +180,7 @@
 	ldr	r0, OMAP5910_MPU_CLKM_BASE	@ base of CLOCK unit
 	mov	r1, #(1 << 10)			@ disable idle mode do not check
 						@ nWAKEUP pin, other remain active
-	strh	r1, [r0, #0x04] 
+	strh	r1, [r0, #0x04]
 	ldr	r1, _OMAP5910_ARM_EN_CLK
 	strh	r1, [r0, #0x08]
 	mov	r1, #0x003f			@ FLASH.RP not enabled in idle and
@@ -190,7 +190,7 @@
 	ldr     r0, MUX_CONFIG_BASE
 	adr	r1, MUX_CONFIG_VALUES
 	adr	r2, MUX_CONFIG_OFFSETS
-next_mux_cfg:	 
+next_mux_cfg:
 	ldrb	r3, [r2], #1
 	ldr	r4, [r1], #4
 	cmp	r3, #0xff
@@ -237,15 +237,15 @@
 	strh	r1, [r0, #0x34]
 
 	/* Setup clock divisors */
-	ldr	r0, OMAP5910_ULPD_PWR_MNG_BASE	@ base of ULDPL DPLL1 register    
+	ldr	r0, OMAP5910_ULPD_PWR_MNG_BASE	@ base of ULDPL DPLL1 register
 
 	mov	r1, #0x0010			@ set PLL_ENABLE
-	orr	r1, r1, #0x2000			@ set IOB to new locking 
-	strh	r1, [r0]			@ write 
+	orr	r1, r1, #0x2000			@ set IOB to new locking
+	strh	r1, [r0]			@ write
 
 ulocking:
 	ldrh	r1, [r0]			@ get DPLL value
-	tst	r1, #1			      
+	tst	r1, #1
 	beq	ulocking			@ while LOCK not set
 
 	/* EMIF init */
@@ -254,7 +254,7 @@
 	bic	r1, r1, #0x0c			@ pwr down disabled, flash WP
 	orr	r1, r1, #0x01
 	str	r1, [r0, #0x0c]
-	
+
 	ldr	r1, VAL_EMIFS_CS0_CONFIG
 	str	r1, [r0, #0x10]			@ EMIFS_CS0_CONFIG
 	ldr	r1, VAL_EMIFS_CS1_CONFIG