riscv: Add device tree bindings for SPI
This patch adds bindings for the MMC slot and SPI flash on the Sipeed Maix
Bit.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Acked-by: Rick Chen <rick@andestech.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
diff --git a/arch/riscv/dts/k210-maix-bit.dts b/arch/riscv/dts/k210-maix-bit.dts
index c2beec6..e4dea20 100644
--- a/arch/riscv/dts/k210-maix-bit.dts
+++ b/arch/riscv/dts/k210-maix-bit.dts
@@ -152,7 +152,7 @@
pinmux = <K210_FPIOA(26, K210_PCF_SPI1_D1)>,
<K210_FPIOA(27, K210_PCF_SPI1_SCLK)>,
<K210_FPIOA(28, K210_PCF_SPI1_D0)>,
- <K210_FPIOA(29, K210_PCF_GPIOHS13)>;
+ <K210_FPIOA(29, K210_PCF_GPIOHS13)>; /* cs */
};
};
@@ -160,3 +160,47 @@
pinctrl-0 = <&fpioa_dvp>;
pinctrl-names = "default";
};
+
+&spi0 {
+ pinctrl-0 = <&fpioa_spi0>;
+ pinctrl-names = "default";
+ num-cs = <1>;
+ cs-gpios = <&gpio0 20 0>;
+
+ panel@0 {
+ compatible = "sitronix,st7789v";
+ reg = <0>;
+ reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
+ dc-gpios = <&gpio0 22 0>;
+ spi-max-frequency = <15000000>;
+ status = "disabled";
+ };
+};
+
+&spi1 {
+ pinctrl-0 = <&fpioa_spi1>;
+ pinctrl-names = "default";
+ num-cs = <1>;
+ cs-gpios = <&gpio0 13 0>;
+ status = "okay";
+
+ slot@0 {
+ compatible = "mmc-spi-slot";
+ reg = <0>;
+ spi-max-frequency = <25000000>;
+ voltage-ranges = <3300 3300>;
+ broken-cd;
+ };
+};
+
+&spi3 {
+ status = "okay";
+
+ spi-flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ broken-flash-reset;
+ };
+};
diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi
index fce98b0..81b0401 100644
--- a/arch/riscv/dts/k210.dtsi
+++ b/arch/riscv/dts/k210.dtsi
@@ -496,6 +496,8 @@
interrupts = <24>;
clocks = <&sysclk K210_CLK_DVP>;
resets = <&sysrst K210_RST_DVP>;
+ kendryte,sysctl = <&sysctl>;
+ kendryte,misc-offset = <K210_SYSCTL_MISC>;
status = "disabled";
};