diff --git a/arch/arm/cpu/pxa/cpu.c b/arch/arm/cpu/pxa/cpu.c
index c48b2ef..7727554 100644
--- a/arch/arm/cpu/pxa/cpu.c
+++ b/arch/arm/cpu/pxa/cpu.c
@@ -234,21 +234,21 @@
 	writel(CONFIG_SYS_GPSR0_VAL, GPSR0);
 	writel(CONFIG_SYS_GPSR1_VAL, GPSR1);
 	writel(CONFIG_SYS_GPSR2_VAL, GPSR2);
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 	writel(CONFIG_SYS_GPSR3_VAL, GPSR3);
 #endif
 
 	writel(CONFIG_SYS_GPCR0_VAL, GPCR0);
 	writel(CONFIG_SYS_GPCR1_VAL, GPCR1);
 	writel(CONFIG_SYS_GPCR2_VAL, GPCR2);
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 	writel(CONFIG_SYS_GPCR3_VAL, GPCR3);
 #endif
 
 	writel(CONFIG_SYS_GPDR0_VAL, GPDR0);
 	writel(CONFIG_SYS_GPDR1_VAL, GPDR1);
 	writel(CONFIG_SYS_GPDR2_VAL, GPDR2);
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 	writel(CONFIG_SYS_GPDR3_VAL, GPDR3);
 #endif
 
@@ -258,7 +258,7 @@
 	writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U);
 	writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L);
 	writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U);
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 	writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L);
 	writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U);
 #endif
@@ -270,7 +270,7 @@
 {
 	writel(0, ICLR);
 	writel(0, ICMR);
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 	writel(0, ICLR2);
 	writel(0, ICMR2);
 #endif
diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S
index 6504819..ba0de8f 100644
--- a/arch/arm/cpu/pxa/start.S
+++ b/arch/arm/cpu/pxa/start.S
@@ -39,7 +39,7 @@
 #include <config.h>
 #include <version.h>
 
-#ifdef CONFIG_PXA25X
+#ifdef CONFIG_CPU_PXA25X
 #if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800)
 #error "Init SP address must be set to 0xfffff800 for PXA250"
 #endif
@@ -160,7 +160,7 @@
 	bl  cpu_init_crit
 #endif
 
-#ifdef	CONFIG_PXA250
+#ifdef	CONFIG_CPU_PXA25X
 	bl	lock_cache_for_stack
 #endif
 
@@ -191,7 +191,7 @@
 	mov	sp, r4
 
 /* Disable the Dcache RAM lock for stack now */
-#ifdef	CONFIG_PXA250
+#ifdef	CONFIG_CPU_PXA25X
 	bl	cpu_init_crit
 #endif
 
@@ -307,7 +307,7 @@
  *
  *************************************************************************
  */
-#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_PXA250)
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
 cpu_init_crit:
 	/*
 	 * flush v4 I/D caches
@@ -327,7 +327,7 @@
 	mcr	p15, 0, r0, c1, c0, 0
 
 	mov	pc, lr		/* back to my caller */
-#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_PXA250 */
+#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */
 
 #ifndef CONFIG_SPL_BUILD
 /*
@@ -519,7 +519,7 @@
  * This is useful on PXA25x and PXA26x in early bootstages, where there is no
  * other possible memory available to hold stack.
  */
-#ifdef CONFIG_PXA250
+#ifdef CONFIG_CPU_PXA25X
 .macro CPWAIT reg
 	mrc	p15, 0, \reg, c2, c0, 0
 	mov	\reg, \reg
@@ -602,4 +602,4 @@
 
 	/* 0xfff00000 : 1:1, cached mapping */
 	.word	(0xfff << 20) | 0x1c1e
-#endif	/* CONFIG_PXA250 */
+#endif	/* CONFIG_CPU_PXA25X */
diff --git a/arch/arm/cpu/pxa/timer.c b/arch/arm/cpu/pxa/timer.c
index 2866745..0ad64dd 100644
--- a/arch/arm/cpu/pxa/timer.c
+++ b/arch/arm/cpu/pxa/timer.c
@@ -35,9 +35,9 @@
 #error: interrupts not implemented yet
 #endif
 
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 #define TIMER_FREQ_HZ 3250000
-#elif defined(CONFIG_PXA250)
+#elif defined(CONFIG_CPU_PXA25X)
 #define TIMER_FREQ_HZ 3686400
 #else
 #error "Timer frequency unknown - please config PXA CPU type"
diff --git a/arch/arm/cpu/pxa/usb.c b/arch/arm/cpu/pxa/usb.c
index 0311d5e..83022e2 100644
--- a/arch/arm/cpu/pxa/usb.c
+++ b/arch/arm/cpu/pxa/usb.c
@@ -24,7 +24,7 @@
 #include <common.h>
 
 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
-# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
+# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X)
 
 #include <asm/arch/pxa-regs.h>
 #include <asm/io.h>
@@ -37,7 +37,7 @@
 	writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA);
 	udelay(100);
 #endif
-#if defined(CONFIG_PXA27X)
+#if defined(CONFIG_CPU_PXA27X)
 	/* Enable USB host clock. */
 	writel(readl(CKEN) | CKEN10_USBHOST, CKEN);
 #endif
@@ -58,7 +58,7 @@
 #if defined(CONFIG_CPU_MONAHANS)
 	writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
 #endif
-#if defined(CONFIG_PXA27X)
+#if defined(CONFIG_CPU_PXA27X)
 	writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR);
 #endif
 	writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR);
@@ -78,7 +78,7 @@
 #if defined(CONFIG_CPU_MONAHANS)
 	writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR);
 #endif
-#if defined(CONFIG_PXA27X)
+#if defined(CONFIG_CPU_PXA27X)
 	writel(readl(UHCHR) | UHCHR_SSEP2, UHCHR);
 #endif
 	writel(readl(UHCHR) | UHCHR_SSEP1 | UHCHR_SSE, UHCHR);
@@ -88,7 +88,7 @@
 	writel(readl(CKENA) & ~(CKENA_2_USBHOST | CKENA_20_UDC), CKENA);
 	udelay(100);
 #endif
-#if defined(CONFIG_PXA27X)
+#if defined(CONFIG_CPU_PXA27X)
 	/* Disable USB host clock. */
 	writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
 #endif
@@ -101,5 +101,5 @@
 	return usb_cpu_stop();
 }
 
-# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) */
+# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X) */
 #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h
index 52c79a9..8527c68 100644
--- a/arch/arm/include/asm/arch-pxa/pxa-regs.h
+++ b/arch/arm/include/asm/arch-pxa/pxa-regs.h
@@ -109,7 +109,7 @@
 #define DCSR13		0x40000034  /* DMA Control / Status Register for Channel 13 */
 #define DCSR14		0x40000038  /* DMA Control / Status Register for Channel 14 */
 #define DCSR15		0x4000003c  /* DMA Control / Status Register for Channel 15 */
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 #define DCSR16		0x40000040  /* DMA Control / Status Register for Channel 16 */
 #define DCSR17		0x40000044  /* DMA Control / Status Register for Channel 17 */
 #define DCSR18		0x40000048  /* DMA Control / Status Register for Channel 18 */
@@ -126,7 +126,7 @@
 #define DCSR29		0x40000074  /* DMA Control / Status Register for Channel 29 */
 #define DCSR30		0x40000078  /* DMA Control / Status Register for Channel 30 */
 #define DCSR31		0x4000007c  /* DMA Control / Status Register for Channel 31 */
-#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
+#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
 
 #define DCSR(x)		(0x40000000 | ((x) << 2))
 
@@ -134,7 +134,7 @@
 #define DCSR_NODESC	(1 << 30)	/* No-Descriptor Fetch (read / write) */
 #define DCSR_STOPIRQEN	(1 << 29)	/* Stop Interrupt Enable (read / write) */
 
-#if defined(CONFIG_PXA27X) || defined (CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 #define DCSR_EORIRQEN	(1 << 28)	/* End of Receive Interrupt Enable (R/W) */
 #define DCSR_EORJMPEN	(1 << 27)	/* Jump to next descriptor on EOR */
 #define DCSR_EORSTOPEN	(1 << 26)	/* STOP on an EOR */
@@ -438,7 +438,7 @@
 /*
  * USB Device Controller
  */
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 
 #define UDCCR		0x40600000	/* UDC Control Register */
 #define UDCCR_UDE	(1 << 0)		/* UDC enable */
@@ -797,9 +797,9 @@
 #define UDCCSR_WR_MASK		(UDCCSR_DME|UDCCSR_FST)
 #define UDC_BCR_MASK		(0x3ff)
 
-#endif /* CONFIG_PXA27X */
+#endif /* CONFIG_CPU_PXA27X */
 
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 
 /******************************************************************************/
 /*
@@ -870,7 +870,7 @@
 #define UP2OCR_CPVPE	(1<<1)
 #define UP2OCR_CPVEN	(1<<0)
 
-#endif	/* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
+#endif	/* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
 
 /******************************************************************************/
 /*
@@ -923,7 +923,7 @@
 #define OWER		0x40A00018  /* OS Timer Watchdog Enable Register */
 #define OIER		0x40A0001C  /* OS Timer Interrupt Enable Register */
 
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 #define OSCR4		0x40A00040  /* OS Timer Counter Register 4 */
 #define OSCR5		0x40A00044  /* OS Timer Counter Register 5 */
 #define OSCR6		0x40A00048  /* OS Timer Counter Register 6 */
@@ -951,7 +951,7 @@
 #define OMCR10		0x40A000D8  /* OS Match Control Register 10 */
 #define OMCR11		0x40A000DC  /* OS Match Control Register 11 */
 
-#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
+#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
 
 #define OSSR_M4		(1 << 4)	/* Match status channel 4 */
 #define OSSR_M3		(1 << 3)	/* Match status channel 3 */
@@ -1052,7 +1052,7 @@
 #define CKEN4_SSP3	(1 << 4)  /* SSP3 Unit Clock Enable */
 
 #define CCCR_N_MASK	0x0380		/* Run Mode Frequency to Turbo Mode Frequency Multiplier */
-#if !defined(CONFIG_PXA27X)
+#if !defined(CONFIG_CPU_PXA27X)
 #define CCCR_M_MASK	0x0060		/* Memory Frequency to Run Mode Frequency Multiplier */
 #endif
 #define CCCR_L_MASK	0x001f		/* Crystal Frequency to Memory Frequency Multiplier */
@@ -1071,7 +1071,7 @@
 #define CKEN13_FICP	(1 << 13)	/* FICP Unit Clock Enable */
 #define CKEN12_MMC	(1 << 12)	/* MMC Unit Clock Enable */
 #define CKEN11_USB	(1 << 11)	/* USB Unit Clock Enable */
-#if defined(CONFIG_PXA27X)
+#if defined(CONFIG_CPU_PXA27X)
 #define CKEN10_USBHOST	(1 << 10)	/* USB Host Unit Clock Enable */
 #define CKEN24_CAMERA	(1 << 24)	/* Camera Unit Clock Enable */
 #endif
@@ -1087,7 +1087,7 @@
 #define OSCC_OON	(1 << 1)	/* 32.768kHz OON (write-once only bit) */
 #define OSCC_OOK	(1 << 0)	/* 32.768kHz OOK (read-only bit) */
 
-#if !defined(CONFIG_PXA27X)
+#if !defined(CONFIG_CPU_PXA27X)
 #define	 CCCR_L09      (0x1F)
 #define	 CCCR_L27      (0x1)
 #define	 CCCR_L32      (0x2)
@@ -1120,7 +1120,7 @@
 #define PWM_PWDUTY1	0x40C00004  /* PWM 1 Duty Cycle Register */
 #define PWM_PERVAL1	0x40C00008  /* PWM 1 Period Control Register */
 
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 #define PWM_CTRL2	0x40B00010  /* PWM 2 Control Register */
 #define PWM_PWDUTY2	0x40B00014  /* PWM 2 Duty Cycle Register */
 #define PWM_PERVAL2	0x40B00018  /* PWM 2 Period Control Register */
@@ -1128,7 +1128,7 @@
 #define PWM_CTRL3	0x40C00010  /* PWM 3 Control Register */
 #define PWM_PWDUTY3	0x40C00014  /* PWM 3 Duty Cycle Register */
 #define PWM_PERVAL3	0x40C00018  /* PWM 3 Period Control Register */
-#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
+#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
 
 /*
  * Interrupt Controller
@@ -1140,14 +1140,14 @@
 #define ICPR		0x40D00010  /* Interrupt Controller Pending Register */
 #define ICCR		0x40D00014  /* Interrupt Controller Control Register */
 
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 #define ICHP		0x40D00018  /* Interrupt Controller Highest Priority Register */
 #define ICIP2		0x40D0009C  /* Interrupt Controller IRQ Pending Register 2 */
 #define ICMR2		0x40D000A0  /* Interrupt Controller Mask Register 2 */
 #define ICLR2		0x40D000A4  /* Interrupt Controller Level Register 2 */
 #define ICFP2		0x40D000A8  /* Interrupt Controller FIQ Pending Register 2 */
 #define ICPR2		0x40D000AC  /* Interrupt Controller Pending Register 2 */
-#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
+#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
 
 /******************************************************************************/
 /*
@@ -1188,7 +1188,7 @@
 #define GAFR2_L		0x40E00064  /* GPIO Alternate Function Select Register GPIO<79:64> */
 #define GAFR2_U		0x40E00068  /* GPIO Alternate Function Select Register GPIO 80 */
 
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 #define GPLR3		0x40E00100  /* GPIO Pin-Level Register GPIO<127:96> */
 #define GPDR3		0x40E0010C  /* GPIO Pin Direction Register GPIO<127:96> */
 #define GPSR3		0x40E00118  /* GPIO Pin Output Set Register GPIO<127:96> */
@@ -1198,7 +1198,7 @@
 #define GEDR3		0x40E00148  /* GPIO Edge Detect Status Register GPIO<127:96> */
 #define GAFR3_L		0x40E0006C  /* GPIO Alternate Function Select Register GPIO<111:96> */
 #define GAFR3_U		0x40E00070  /* GPIO Alternate Function Select Register GPIO<127:112> */
-#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
+#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
 
 #ifdef CONFIG_CPU_MONAHANS
 #define GSDR0		0x40E00400 /* Bit-wise Set of GPDR[31:0] */
@@ -1244,7 +1244,7 @@
 #define _GEDR(x)	(0x40E00048 + (((x) & 0x60) >> 3))
 #define _GAFR(x)	(0x40E00054 + (((x) & 0x70) >> 2))
 
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 #define GPLR(x)		(((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3))
 #define GPDR(x)		(((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3))
 #define GPSR(x)		(((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3))
@@ -2123,7 +2123,7 @@
 #define LCCR0_PDD_S	12
 #define LCCR0_BM	(1 << 20)	/* Branch mask */
 #define LCCR0_OUM	(1 << 21)	/* Output FIFO underrun mask */
-#if defined(CONFIG_PXA27X)
+#if defined(CONFIG_CPU_PXA27X)
 #define LCCR0_LCDT	(1 << 22)	/* LCD Panel Type */
 #define LCCR0_RDSTM	(1 << 23)	/* Read Status Interrupt Mask */
 #define LCCR0_CMDIM	(1 << 24)	/* Command Interrupt Mask */
@@ -2249,7 +2249,7 @@
 #define LCSR1_IU6	(1 << 29)
 
 #define LDCMD_PAL	(1 << 26)	/* instructs DMA to load palette buffer */
-#if defined(CONFIG_PXA27X)
+#if defined(CONFIG_CPU_PXA27X)
 #define LDCMD_SOFINT	(1 << 22)
 #define LDCMD_EOFINT	(1 << 21)
 #endif
@@ -2480,7 +2480,7 @@
 #define MDREFR_K0RUN	(1 << 13)	/* SDCLK0 Run Control/Status */
 #define MDREFR_E0PIN	(1 << 12)	/* SDCKE0 Level Control/Status */
 
-#if defined(CONFIG_PXA27X)
+#if defined(CONFIG_CPU_PXA27X)
 
 #define ARB_CNTRL	0x48000048  /* Arbiter Control Register */
 
@@ -2494,7 +2494,7 @@
 #define ARB_CORE_PARK		(1<<24)	   /* Be parked with core when idle */
 #define ARB_LOCK_FLAG		(1<<23)	   /* Only Locking masters gain access to the bus */
 
-#endif /* CONFIG_PXA27X */
+#endif /* CONFIG_CPU_PXA27X */
 
 /* LCD registers */
 #define LCCR4		0x44000010  /* LCD Controller Control Register 4 */
@@ -2628,6 +2628,6 @@
 #define OSCR4		0x40A00040  /* OS Timer Counter Register */
 #define OMCR4		0x40A000C0  /* */
 
-#endif	/* CONFIG_PXA27X */
+#endif	/* CONFIG_CPU_PXA27X */
 
 #endif	/* _PXA_REGS_H_ */