| commit | ab2a98b11716364bc5a8c43cdfa7fee176cda1d8 | [log] [tgz] |
|---|---|---|
| author | Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> | Wed Jul 27 13:22:38 2011 +0200 |
| committer | Shinya Kuribayashi <skuribay@pobox.com> | Sun Jul 31 23:26:41 2011 +0900 |
| tree | f6d237d468eec036180a987fa99a8f58aa907e89 | |
| parent | 7185adb48ef1e5b0f05263a7f791de340ddddeb2 [diff] |
MIPS: make cache operation mode configurable Currently the cache operation mode is hard-coded to CONF_CM_CACHABLE_NONCOHERENT. This is not appropiate for CPUs or SOCs which operate at a different mode. This patch makes the cache operation mode configurable via board config. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Acked-by: Thomas Langer <thomas.langer@lantiq.com> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>