| commit | 9b7aac75365b68bae2e8f7cf074ba95638d31882 | [log] [tgz] |
|---|---|---|
| author | Michal Simek <michal.simek@xilinx.com> | Tue Feb 09 15:28:15 2021 +0100 |
| committer | Michal Simek <michal.simek@xilinx.com> | Tue Feb 23 14:56:59 2021 +0100 |
| tree | 9d2ee4b001275fe6a2191ead6ec3913e033a783d | |
| parent | 3aba25bc382beeb8a92b46d23fd1db47dfcb1121 [diff] |
clk: zynq: Add dummy clock enable function
A lot of Xilinx drivers are checking -ENOSYS which means that clock driver
doesn't have enable function. Remove this checking from drivers and create
dummy enable function as was done for clk_fixed_rate driver by
commit 6bf6d81c1112 ("clk: fixed_rate: add dummy enable() function").
Signed-off-by: Michal Simek <michal.simek@xilinx.com>