diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile
index 4a00757..aedc395 100644
--- a/arch/x86/cpu/ivybridge/Makefile
+++ b/arch/x86/cpu/ivybridge/Makefile
@@ -18,3 +18,4 @@
 obj-y += sata.o
 obj-y += sdram.o
 obj-y += usb_ehci.o
+obj-y += usb_xhci.o
diff --git a/arch/x86/cpu/ivybridge/usb_xhci.c b/arch/x86/cpu/ivybridge/usb_xhci.c
new file mode 100644
index 0000000..4a32a7e
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/usb_xhci.c
@@ -0,0 +1,32 @@
+/*
+ * From Coreboot
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+
+void bd82x6x_usb_xhci_init(pci_dev_t dev)
+{
+	u32 reg32;
+
+	debug("XHCI: Setting up controller.. ");
+
+	/* lock overcurrent map */
+	reg32 = pci_read_config32(dev, 0x44);
+	reg32 |= 1;
+	pci_write_config32(dev, 0x44, reg32);
+
+	/* Enable clock gating */
+	reg32 = pci_read_config32(dev, 0x40);
+	reg32 &= ~((1 << 20) | (1 << 21));
+	reg32 |= (1 << 19) | (1 << 18) | (1 << 17);
+	reg32 |= (1 << 10) | (1 << 9) | (1 << 8);
+	reg32 |= (1 << 31); /* lock */
+	pci_write_config32(dev, 0x40, reg32);
+
+	debug("done.\n");
+}
diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
index 2e6a079..6454dd9 100644
--- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
+++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
@@ -11,6 +11,7 @@
 void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node);
 void bd82x6x_pci_init(pci_dev_t dev);
 void bd82x6x_usb_ehci_init(pci_dev_t dev);
+void bd82x6x_usb_xhci_init(pci_dev_t dev);
 int bd82x6x_init_pci_devices(void);
 int bd82x6x_init(void);