mpc83xx: Add strider board
The gdsys strider board is based on a Freescale MPC8308 SOC.
It boots from NOR-Flash, kernel and rootfs are stored on
SD-Card.
On board peripherals include:
- 1x 10/100 Mbit/s Ethernet (optional)
- Lattice ECP3 FPGA connected via eLBC
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
[trini: Drop setting CONFIG_SYS_GENERIC_BOARD, this is always true now]
Signed-off-by: Tom Rini <trini@konsulko.com>
diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile
index 95e41de..ba48e8b 100644
--- a/board/gdsys/common/Makefile
+++ b/board/gdsys/common/Makefile
@@ -9,7 +9,9 @@
obj-$(CONFIG_CMD_IOLOOP) += cmd_ioloop.o
obj-$(CONFIG_IO) += miiphybb.o
obj-$(CONFIG_IO64) += miiphybb.o
-obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o phy.o
+obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o phy.o ch7301.o
obj-$(CONFIG_DLVISION_10G) += osd.o dp501.o
obj-$(CONFIG_CONTROLCENTERD) += dp501.o
obj-$(CONFIG_HRCON) += osd.o mclink.o dp501.o phy.o
+obj-$(CONFIG_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o
+obj-$(CONFIG_STRIDER_CON) += osd.o
diff --git a/board/gdsys/common/adv7611.c b/board/gdsys/common/adv7611.c
new file mode 100644
index 0000000..b728274
--- /dev/null
+++ b/board/gdsys/common/adv7611.c
@@ -0,0 +1,177 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#define ADV7611_I2C_ADDR 0x4c
+#define ADV7611_RDINFO 0x2051
+
+/*
+ * ADV7611 I2C Addresses in u-boot notation
+ */
+enum {
+ CP_I2C_ADDR = 0x22,
+ DPLL_I2C_ADDR = 0x26,
+ KSV_I2C_ADDR = 0x32,
+ HDMI_I2C_ADDR = 0x34,
+ EDID_I2C_ADDR = 0x36,
+ INFOFRAME_I2C_ADDR = 0x3e,
+ CEC_I2C_ADDR = 0x40,
+ IO_I2C_ADDR = ADV7611_I2C_ADDR,
+};
+
+/*
+ * Global Control Registers
+ */
+enum {
+ IO_RD_INFO_MSB = 0xea,
+ IO_RD_INFO_LSB = 0xeb,
+ IO_CEC_ADDR = 0xf4,
+ IO_INFOFRAME_ADDR = 0xf5,
+ IO_DPLL_ADDR = 0xf8,
+ IO_KSV_ADDR = 0xf9,
+ IO_EDID_ADDR = 0xfa,
+ IO_HDMI_ADDR = 0xfb,
+ IO_CP_ADDR = 0xfd,
+};
+
+int adv7611_i2c[] = CONFIG_SYS_ADV7611_I2C;
+
+int adv7611_probe(unsigned int screen)
+{
+ int old_bus = i2c_get_bus_num();
+ unsigned int rd_info;
+ int res = 0;
+
+ i2c_set_bus_num(adv7611_i2c[screen]);
+
+ rd_info = (i2c_reg_read(IO_I2C_ADDR, IO_RD_INFO_MSB) << 8)
+ | i2c_reg_read(IO_I2C_ADDR, IO_RD_INFO_LSB);
+
+ if (rd_info != ADV7611_RDINFO) {
+ res = -1;
+ goto out;
+ }
+
+ /*
+ * set I2C addresses to default values
+ */
+ i2c_reg_write(IO_I2C_ADDR, IO_CEC_ADDR, CEC_I2C_ADDR << 1);
+ i2c_reg_write(IO_I2C_ADDR, IO_INFOFRAME_ADDR, INFOFRAME_I2C_ADDR << 1);
+ i2c_reg_write(IO_I2C_ADDR, IO_DPLL_ADDR, DPLL_I2C_ADDR << 1);
+ i2c_reg_write(IO_I2C_ADDR, IO_KSV_ADDR, KSV_I2C_ADDR << 1);
+ i2c_reg_write(IO_I2C_ADDR, IO_EDID_ADDR, EDID_I2C_ADDR << 1);
+ i2c_reg_write(IO_I2C_ADDR, IO_HDMI_ADDR, HDMI_I2C_ADDR << 1);
+ i2c_reg_write(IO_I2C_ADDR, IO_CP_ADDR, CP_I2C_ADDR << 1);
+
+ /*
+ * do magic initialization sequence from
+ * "ADV7611 Register Settings Recommendations Revision 1.5"
+ * with most registers undocumented
+ */
+ i2c_reg_write(CP_I2C_ADDR, 0x6c, 0x00);
+ i2c_reg_write(HDMI_I2C_ADDR, 0x9b, 0x03);
+ i2c_reg_write(HDMI_I2C_ADDR, 0x6f, 0x08);
+ i2c_reg_write(HDMI_I2C_ADDR, 0x85, 0x1f);
+ i2c_reg_write(HDMI_I2C_ADDR, 0x87, 0x70);
+ i2c_reg_write(HDMI_I2C_ADDR, 0x57, 0xda);
+ i2c_reg_write(HDMI_I2C_ADDR, 0x58, 0x01);
+ i2c_reg_write(HDMI_I2C_ADDR, 0x03, 0x98);
+ i2c_reg_write(HDMI_I2C_ADDR, 0x4c, 0x44);
+
+ /*
+ * IO_REG_02, default 0xf0
+ *
+ * INP_COLOR_SPACE (IO, Address 0x02[7:4])
+ * default: 0b1111 auto
+ * set to : 0b0001 force RGB (range 0 to 255) input
+ *
+ * RGB_OUT (IO, Address 0x02[1])
+ * default: 0 YPbPr color space output
+ * set to : 1 RGB color space output
+ */
+ i2c_reg_write(IO_I2C_ADDR, 0x02, 0x12);
+
+ /*
+ * IO_REG_03, default 0x00
+ *
+ * OP_FORMAT_SEL (IO, Address 0x03[7:0])
+ * default: 0x00 8-bit SDR ITU-656 mode
+ * set to : 0x40 24-bit 4:4:4 SDR mode
+ */
+ i2c_reg_write(IO_I2C_ADDR, 0x03, 0x40);
+
+ /*
+ * IO_REG_05, default 0x2c
+ *
+ * AVCODE_INSERT_EN (IO, Address 0x05[2])
+ * default: 1 insert AV codes into data stream
+ * set to : 0 do not insert AV codes into data stream
+ */
+ i2c_reg_write(IO_I2C_ADDR, 0x05, 0x28);
+
+ /*
+ * IO_REG_0C, default 0x62
+ *
+ * POWER_DOWN (IO, Address 0x0C[5])
+ * default: 1 chip is powered down
+ * set to : 0 chip is operational
+ */
+ i2c_reg_write(IO_I2C_ADDR, 0x0c, 0x42);
+
+ /*
+ * IO_REG_15, default 0xbe
+ *
+ * TRI_SYNCS (IO, Address 0x15[3)
+ * TRI_LLC (IO, Address 0x15[2])
+ * TRI_PIX (IO, Address 0x15[1])
+ * default: 1 video output pins are tristate
+ * set to : 0 video output pins are active
+ */
+ i2c_reg_write(IO_I2C_ADDR, 0x15, 0xb0);
+
+ /*
+ * HDMI_REGISTER_02H, default 0xff
+ *
+ * CLOCK_TERMA_DISABLE (HDMI, Address 0x83[0])
+ * default: 1 disable termination
+ * set to : 0 enable termination
+ * Future options are:
+ * - use the chips automatic termination control
+ * - set this manually on cable detect
+ * but at the moment this seems a safe default.
+ */
+ i2c_reg_write(HDMI_I2C_ADDR, 0x83, 0xfe);
+
+ /*
+ * HDMI_CP_CNTRL_1, default 0x01
+ *
+ * HDMI_FRUN_EN (CP, Address 0xBA[0])
+ * default: 1 Enable the free run feature in HDMI mode
+ * set to : 0 Disable the free run feature in HDMI mode
+ */
+ i2c_reg_write(CP_I2C_ADDR, 0xba, 0x00);
+
+ /*
+ * INT1_CONFIGURATION, default 0x20
+ *
+ * INTRQ_DUR_SEL[1:0] (IO, Address 0x40[7:6])
+ * default: 00 Interrupt signal is active for 4 Xtal periods
+ * set to : 11 Active until cleared
+ *
+ * INTRQ_OP_SEL[1:0] (IO, Address 0x40[1:0])
+ * default: 00 Open drain
+ * set to : 10 Drives high when active
+ */
+ i2c_reg_write(IO_I2C_ADDR, 0x40, 0xc2);
+
+out:
+ i2c_set_bus_num(old_bus);
+
+ return res;
+}
diff --git a/board/gdsys/common/adv7611.h b/board/gdsys/common/adv7611.h
new file mode 100644
index 0000000..25a8367
--- /dev/null
+++ b/board/gdsys/common/adv7611.h
@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ADV7611_H_
+#define _ADV7611_H_
+
+int adv7611_probe(unsigned int screen);
+
+#endif
diff --git a/board/gdsys/common/ch7301.c b/board/gdsys/common/ch7301.c
new file mode 100644
index 0000000..c054e55
--- /dev/null
+++ b/board/gdsys/common/ch7301.c
@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Chrontel CH7301C DVI Transmitter */
+
+#include <common.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <i2c.h>
+
+#define CH7301_I2C_ADDR 0x75
+
+enum {
+ CH7301_CM = 0x1c, /* Clock Mode Register */
+ CH7301_IC = 0x1d, /* Input Clock Register */
+ CH7301_GPIO = 0x1e, /* GPIO Control Register */
+ CH7301_IDF = 0x1f, /* Input Data Format Register */
+ CH7301_CD = 0x20, /* Connection Detect Register */
+ CH7301_DC = 0x21, /* DAC Control Register */
+ CH7301_HPD = 0x23, /* Hot Plug Detection Register */
+ CH7301_TCTL = 0x31, /* DVI Control Input Register */
+ CH7301_TPCP = 0x33, /* DVI PLL Charge Pump Ctrl Register */
+ CH7301_TPD = 0x34, /* DVI PLL Divide Register */
+ CH7301_TPVT = 0x35, /* DVI PLL Supply Control Register */
+ CH7301_TPF = 0x36, /* DVI PLL Filter Register */
+ CH7301_TCT = 0x37, /* DVI Clock Test Register */
+ CH7301_TSTP = 0x48, /* Test Pattern Register */
+ CH7301_PM = 0x49, /* Power Management register */
+ CH7301_VID = 0x4a, /* Version ID Register */
+ CH7301_DID = 0x4b, /* Device ID Register */
+ CH7301_DSP = 0x56, /* DVI Sync polarity Register */
+};
+
+int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C;
+
+int ch7301_probe(unsigned screen, bool power)
+{
+ u8 value;
+
+ i2c_set_bus_num(ch7301_i2c[screen]);
+ if (i2c_probe(CH7301_I2C_ADDR))
+ return -1;
+
+ value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
+ if (value != 0x17)
+ return -1;
+
+ if (power) {
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
+ } else {
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x00);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0x01);
+ }
+
+ return 0;
+}
diff --git a/board/gdsys/common/ch7301.h b/board/gdsys/common/ch7301.h
new file mode 100644
index 0000000..8383719
--- /dev/null
+++ b/board/gdsys/common/ch7301.h
@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CH7301_H_
+#define _CH7301_H_
+
+int ch7301_probe(unsigned screen, bool power);
+
+#endif
diff --git a/board/gdsys/common/ioep-fpga.c b/board/gdsys/common/ioep-fpga.c
new file mode 100644
index 0000000..18d37dc
--- /dev/null
+++ b/board/gdsys/common/ioep-fpga.c
@@ -0,0 +1,227 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <gdsys_fpga.h>
+
+enum {
+ UNITTYPE_MAIN_SERVER = 0,
+ UNITTYPE_MAIN_USER = 1,
+ UNITTYPE_VIDEO_SERVER = 2,
+ UNITTYPE_VIDEO_USER = 3,
+};
+
+enum {
+ UNITTYPEPCB_DVI = 0,
+ UNITTYPEPCB_DP_165 = 1,
+ UNITTYPEPCB_DP_300 = 2,
+ UNITTYPEPCB_HDMI = 3,
+};
+
+enum {
+ COMPRESSION_NONE = 0,
+ COMPRESSION_TYPE1_DELTA = 1,
+ COMPRESSION_TYPE1_TYPE2_DELTA = 3,
+};
+
+enum {
+ AUDIO_NONE = 0,
+ AUDIO_TX = 1,
+ AUDIO_RX = 2,
+ AUDIO_RXTX = 3,
+};
+
+enum {
+ SYSCLK_147456 = 0,
+};
+
+enum {
+ RAM_DDR2_32 = 0,
+ RAM_DDR3_32 = 1,
+};
+
+enum {
+ CARRIER_SPEED_1G = 0,
+ CARRIER_SPEED_2_5G = 1,
+};
+
+bool ioep_fpga_has_osd(unsigned int fpga)
+{
+ u16 fpga_features;
+ unsigned feature_osd;
+
+ FPGA_GET_REG(0, fpga_features, &fpga_features);
+ feature_osd = fpga_features & (1<<11);
+
+ return feature_osd;
+}
+
+void ioep_fpga_print_info(unsigned int fpga)
+{
+ u16 versions;
+ u16 fpga_version;
+ u16 fpga_features;
+ unsigned unit_type;
+ unsigned unit_type_pcb_video;
+ unsigned feature_compression;
+ unsigned feature_osd;
+ unsigned feature_audio;
+ unsigned feature_sysclock;
+ unsigned feature_ramconfig;
+ unsigned feature_carrier_speed;
+ unsigned feature_carriers;
+ unsigned feature_video_channels;
+
+ FPGA_GET_REG(fpga, versions, &versions);
+ FPGA_GET_REG(fpga, fpga_version, &fpga_version);
+ FPGA_GET_REG(fpga, fpga_features, &fpga_features);
+
+ unit_type = (versions & 0xf000) >> 12;
+ unit_type_pcb_video = (versions & 0x01c0) >> 6;
+ feature_compression = (fpga_features & 0xe000) >> 13;
+ feature_osd = fpga_features & (1<<11);
+ feature_audio = (fpga_features & 0x0600) >> 9;
+ feature_sysclock = (fpga_features & 0x0180) >> 7;
+ feature_ramconfig = (fpga_features & 0x0060) >> 5;
+ feature_carrier_speed = fpga_features & (1<<4);
+ feature_carriers = (fpga_features & 0x000c) >> 2;
+ feature_video_channels = fpga_features & 0x0003;
+
+ switch (unit_type) {
+ case UNITTYPE_MAIN_SERVER:
+ case UNITTYPE_MAIN_USER:
+ printf("Mainchannel");
+ break;
+
+ case UNITTYPE_VIDEO_SERVER:
+ case UNITTYPE_VIDEO_USER:
+ printf("Videochannel");
+ break;
+
+ default:
+ printf("UnitType %d(not supported)", unit_type);
+ break;
+ }
+
+ switch (unit_type) {
+ case UNITTYPE_MAIN_SERVER:
+ case UNITTYPE_VIDEO_SERVER:
+ printf(" Server");
+ if (versions & (1<<4))
+ printf(" UC");
+ break;
+
+ case UNITTYPE_MAIN_USER:
+ case UNITTYPE_VIDEO_USER:
+ printf(" User");
+ break;
+
+ default:
+ break;
+ }
+
+ if (versions & (1<<5))
+ printf(" Fiber");
+ else
+ printf(" CAT");
+
+ switch (unit_type_pcb_video) {
+ case UNITTYPEPCB_DVI:
+ printf(" DVI,");
+ break;
+
+ case UNITTYPEPCB_DP_165:
+ printf(" DP 165MPix/s,");
+ break;
+
+ case UNITTYPEPCB_DP_300:
+ printf(" DP 300MPix/s,");
+ break;
+
+ case UNITTYPEPCB_HDMI:
+ printf(" HDMI,");
+ break;
+ }
+
+ printf(" FPGA V %d.%02d\n features:",
+ fpga_version / 100, fpga_version % 100);
+
+
+ switch (feature_compression) {
+ case COMPRESSION_NONE:
+ printf(" no compression");
+ break;
+
+ case COMPRESSION_TYPE1_DELTA:
+ printf(" type1-deltacompression");
+ break;
+
+ case COMPRESSION_TYPE1_TYPE2_DELTA:
+ printf(" type1-deltacompression, type2-inlinecompression");
+ break;
+
+ default:
+ printf(" compression %d(not supported)", feature_compression);
+ break;
+ }
+
+ printf(", %sosd", feature_osd ? "" : "no ");
+
+ switch (feature_audio) {
+ case AUDIO_NONE:
+ printf(", no audio");
+ break;
+
+ case AUDIO_TX:
+ printf(", audio tx");
+ break;
+
+ case AUDIO_RX:
+ printf(", audio rx");
+ break;
+
+ case AUDIO_RXTX:
+ printf(", audio rx+tx");
+ break;
+
+ default:
+ printf(", audio %d(not supported)", feature_audio);
+ break;
+ }
+
+ puts(",\n ");
+
+ switch (feature_sysclock) {
+ case SYSCLK_147456:
+ printf("clock 147.456 MHz");
+ break;
+
+ default:
+ printf("clock %d(not supported)", feature_sysclock);
+ break;
+ }
+
+ switch (feature_ramconfig) {
+ case RAM_DDR2_32:
+ printf(", RAM 32 bit DDR2");
+ break;
+
+ case RAM_DDR3_32:
+ printf(", RAM 32 bit DDR3");
+ break;
+
+ default:
+ printf(", RAM %d(not supported)", feature_ramconfig);
+ break;
+ }
+
+ printf(", %d carrier(s) %s", feature_carriers,
+ feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s");
+
+ printf(", %d video channel(s)\n", feature_video_channels);
+}
diff --git a/board/gdsys/common/ioep-fpga.h b/board/gdsys/common/ioep-fpga.h
new file mode 100644
index 0000000..44f7139
--- /dev/null
+++ b/board/gdsys/common/ioep-fpga.h
@@ -0,0 +1,14 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _IOEP_FPGA_H_
+#define _IOEP_FPGA_H_
+
+void ioep_fpga_print_info(unsigned int fpga);
+bool ioep_fpga_has_osd(unsigned int fpga);
+
+#endif
diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c
index 55ecdf1..f11e26f 100644
--- a/board/gdsys/common/osd.c
+++ b/board/gdsys/common/osd.c
@@ -9,11 +9,10 @@
#include <i2c.h>
#include <malloc.h>
+#include "ch7301.h"
#include "dp501.h"
#include <gdsys_fpga.h>
-#define CH7301_I2C_ADDR 0x75
-
#define ICS8N3QV01_I2C_ADDR 0x6E
#define ICS8N3QV01_FREF 114285000
#define ICS8N3QV01_FREF_LL 114285000LL
@@ -29,27 +28,6 @@
#define PIXCLK_640_480_60 25180000
-enum {
- CH7301_CM = 0x1c, /* Clock Mode Register */
- CH7301_IC = 0x1d, /* Input Clock Register */
- CH7301_GPIO = 0x1e, /* GPIO Control Register */
- CH7301_IDF = 0x1f, /* Input Data Format Register */
- CH7301_CD = 0x20, /* Connection Detect Register */
- CH7301_DC = 0x21, /* DAC Control Register */
- CH7301_HPD = 0x23, /* Hot Plug Detection Register */
- CH7301_TCTL = 0x31, /* DVI Control Input Register */
- CH7301_TPCP = 0x33, /* DVI PLL Charge Pump Ctrl Register */
- CH7301_TPD = 0x34, /* DVI PLL Divide Register */
- CH7301_TPVT = 0x35, /* DVI PLL Supply Control Register */
- CH7301_TPF = 0x36, /* DVI PLL Filter Register */
- CH7301_TCT = 0x37, /* DVI Clock Test Register */
- CH7301_TSTP = 0x48, /* Test Pattern Register */
- CH7301_PM = 0x49, /* Power Management register */
- CH7301_VID = 0x4a, /* Version ID Register */
- CH7301_DID = 0x4b, /* Device ID Register */
- CH7301_DSP = 0x56, /* DVI Sync polarity Register */
-};
-
unsigned int base_width;
unsigned int base_height;
size_t bufsize;
@@ -61,10 +39,6 @@
int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C;
#endif
-#ifdef CONFIG_SYS_CH7301_I2C
-int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C;
-#endif
-
#ifdef CONFIG_SYS_SIL1178_I2C
int sil1178_i2c[] = CONFIG_SYS_SIL1178_I2C;
#endif
@@ -327,19 +301,8 @@
/* setup output driver */
#ifdef CONFIG_SYS_CH7301_I2C
- i2c_set_bus_num(ch7301_i2c[screen]);
- if (!i2c_probe(CH7301_I2C_ADDR)) {
- u8 value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
-
- if (value == 0x17) {
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
- output_driver_present = true;
- }
- }
+ if (!ch7301_probe(screen, true))
+ output_driver_present = true;
#endif
#ifdef CONFIG_SYS_SIL1178_I2C
diff --git a/board/gdsys/common/osd.h b/board/gdsys/common/osd.h
index 440b276..5b3f14b 100644
--- a/board/gdsys/common/osd.h
+++ b/board/gdsys/common/osd.h
@@ -8,6 +8,7 @@
#ifndef _OSD_H_
#define _OSD_H_
+int ch7301_probe(unsigned screen, bool power);
int osd_probe(unsigned screen);
#endif
diff --git a/board/gdsys/mpc8308/Kconfig b/board/gdsys/mpc8308/Kconfig
index 43e1663..9a1a3a2 100644
--- a/board/gdsys/mpc8308/Kconfig
+++ b/board/gdsys/mpc8308/Kconfig
@@ -10,3 +10,16 @@
default "hrcon"
endif
+
+if TARGET_STRIDER
+
+config SYS_BOARD
+ default "mpc8308"
+
+config SYS_VENDOR
+ default "gdsys"
+
+config SYS_CONFIG_NAME
+ default "strider"
+
+endif
diff --git a/board/gdsys/mpc8308/MAINTAINERS b/board/gdsys/mpc8308/MAINTAINERS
index a7853a5..35704bc 100644
--- a/board/gdsys/mpc8308/MAINTAINERS
+++ b/board/gdsys/mpc8308/MAINTAINERS
@@ -4,3 +4,6 @@
F: board/gdsys/mpc8308/
F: include/configs/hrcon.h
F: configs/hrcon_defconfig
+F: include/configs/strider.h
+F: configs/strider_cpu_defconfig
+F: configs/strider_con_defconfig
diff --git a/board/gdsys/mpc8308/Makefile b/board/gdsys/mpc8308/Makefile
index b5dfdbb..42702fb 100644
--- a/board/gdsys/mpc8308/Makefile
+++ b/board/gdsys/mpc8308/Makefile
@@ -7,3 +7,4 @@
obj-y := mpc8308.o sdram.o
obj-$(CONFIG_HRCON) += hrcon.o
+obj-$(CONFIG_STRIDER) += strider.o
diff --git a/board/gdsys/mpc8308/strider.c b/board/gdsys/mpc8308/strider.c
new file mode 100644
index 0000000..8e5d5de
--- /dev/null
+++ b/board/gdsys/mpc8308/strider.c
@@ -0,0 +1,501 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <spi.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pci.h>
+#include <mpc83xx.h>
+#include <fsl_esdhc.h>
+#include <asm/io.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_mpc83xx_serdes.h>
+
+#include "mpc8308.h"
+
+#include <gdsys_fpga.h>
+
+#include "../common/adv7611.h"
+#include "../common/ch7301.h"
+#include "../common/ioep-fpga.h"
+#include "../common/mclink.h"
+#include "../common/osd.h"
+#include "../common/phy.h"
+
+#include <pca953x.h>
+#include <pca9698.h>
+
+#include <miiphy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MAX_MUX_CHANNELS 2
+
+enum {
+ MCFPGA_DONE = 1 << 0,
+ MCFPGA_INIT_N = 1 << 1,
+ MCFPGA_PROGRAM_N = 1 << 2,
+ MCFPGA_UPDATE_ENABLE_N = 1 << 3,
+ MCFPGA_RESET_N = 1 << 4,
+};
+
+enum {
+ GPIO_MDC = 1 << 14,
+ GPIO_MDIO = 1 << 15,
+};
+
+enum {
+ FAN_CONFIG = 0x03,
+ FAN_TACHLIM_LSB = 0x48,
+ FAN_TACHLIM_MSB = 0x49,
+ FAN_PWM_FREQ = 0x4D,
+};
+
+unsigned int mclink_fpgacount;
+struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+
+struct {
+ u8 bus;
+ u8 addr;
+} strider_fans[] = CONFIG_STRIDER_FANS;
+
+int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
+{
+ int res;
+
+ switch (fpga) {
+ case 0:
+ out_le16(reg, data);
+ break;
+ default:
+ res = mclink_send(fpga - 1, regoff, data);
+ if (res < 0) {
+ printf("mclink_send reg %02lx data %04x returned %d\n",
+ regoff, data, res);
+ return res;
+ }
+ break;
+ }
+
+ return 0;
+}
+
+int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
+{
+ int res;
+
+ switch (fpga) {
+ case 0:
+ *data = in_le16(reg);
+ break;
+ default:
+ if (fpga > mclink_fpgacount)
+ return -EINVAL;
+ res = mclink_receive(fpga - 1, regoff, data);
+ if (res < 0) {
+ printf("mclink_receive reg %02lx returned %d\n",
+ regoff, res);
+ return res;
+ }
+ }
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+ bool hw_type_cat = pca9698_get_value(0x20, 18);
+
+ puts("Board: ");
+
+ printf("Strider %s", hw_type_cat ? "CAT" : "Fiber");
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+
+ puts("\n");
+
+ return 0;
+}
+
+static void init_fan_controller(u8 addr)
+{
+ int val;
+
+ /* set PWM Frequency to 2.5% resolution */
+ i2c_reg_write(addr, FAN_PWM_FREQ, 20);
+
+ /* set Tachometer Limit */
+ i2c_reg_write(addr, FAN_TACHLIM_LSB, 0x10);
+ i2c_reg_write(addr, FAN_TACHLIM_MSB, 0x0a);
+
+ /* enable Tach input */
+ val = i2c_reg_read(addr, FAN_CONFIG) | 0x04;
+ i2c_reg_write(addr, FAN_CONFIG, val);
+}
+
+int last_stage_init(void)
+{
+ int slaves;
+ unsigned int k;
+ unsigned int mux_ch;
+ unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e };
+ bool hw_type_cat = pca9698_get_value(0x20, 18);
+ bool ch0_sgmii2_present = false;
+
+ /* Turn on Analog Devices ADV7611 */
+ pca9698_direction_output(0x20, 8, 0);
+
+ /* Turn on Parade DP501 */
+ pca9698_direction_output(0x20, 9, 1);
+
+ ch0_sgmii2_present = !pca9698_get_value(0x20, 37);
+
+ /* wait for FPGA done, then reset FPGA */
+ for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
+ unsigned int ctr = 0;
+
+ if (i2c_probe(mclink_controllers[k]))
+ continue;
+
+ while (!(pca953x_get_val(mclink_controllers[k])
+ & MCFPGA_DONE)) {
+ udelay(100000);
+ if (ctr++ > 5) {
+ printf("no done for mclink_controller %d\n", k);
+ break;
+ }
+ }
+
+ pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
+ pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
+ udelay(10);
+ pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
+ MCFPGA_RESET_N);
+ }
+
+ if (hw_type_cat) {
+ miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
+ bb_miiphy_write);
+ for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
+ if ((mux_ch == 1) && !ch0_sgmii2_present)
+ continue;
+
+ setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
+ }
+ }
+
+ /* give slave-PLLs and Parade DP501 some time to be up and running */
+ udelay(500000);
+
+ mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
+ slaves = mclink_probe();
+ mclink_fpgacount = 0;
+
+ ioep_fpga_print_info(0);
+
+ if (!adv7611_probe(0))
+ printf(" Advantiv ADV7611 HDMI Receiver\n");
+
+#ifdef CONFIG_STRIDER_CON
+ if (ioep_fpga_has_osd(0))
+ osd_probe(0);
+#endif
+
+#ifdef CONFIG_STRIDER_CPU
+ ch7301_probe(0, false);
+#endif
+
+ if (slaves <= 0)
+ return 0;
+
+ mclink_fpgacount = slaves;
+
+ for (k = 1; k <= slaves; ++k) {
+ ioep_fpga_print_info(k);
+#ifdef CONFIG_STRIDER_CON
+ if (ioep_fpga_has_osd(k))
+ osd_probe(k);
+#endif
+#ifdef CONFIG_STRIDER_CPU
+ FPGA_SET_REG(k, extended_control, 0); /* enable video in*/
+ if (!adv7611_probe(k))
+ printf(" Advantiv ADV7611 HDMI Receiver\n");
+ ch7301_probe(k, false);
+#endif
+ if (hw_type_cat) {
+ miiphy_register(bb_miiphy_buses[k].name,
+ bb_miiphy_read, bb_miiphy_write);
+ setup_88e1514(bb_miiphy_buses[k].name, 0);
+ }
+ }
+
+ for (k = 0; k < ARRAY_SIZE(strider_fans); ++k) {
+ i2c_set_bus_num(strider_fans[k].bus);
+ init_fan_controller(strider_fans[k].addr);
+ }
+
+ return 0;
+}
+
+/*
+ * provide access to fpga gpios (for I2C bitbang)
+ * (these may look all too simple but make iocon.h much more readable)
+ */
+void fpga_gpio_set(unsigned int bus, int pin)
+{
+ FPGA_SET_REG(bus, gpio.set, pin);
+}
+
+void fpga_gpio_clear(unsigned int bus, int pin)
+{
+ FPGA_SET_REG(bus, gpio.clear, pin);
+}
+
+int fpga_gpio_get(unsigned int bus, int pin)
+{
+ u16 val;
+
+ FPGA_GET_REG(bus, gpio.read, &val);
+
+ return val & pin;
+}
+
+void mpc8308_init(void)
+{
+ pca9698_direction_output(0x20, 26, 1);
+}
+
+void mpc8308_set_fpga_reset(unsigned state)
+{
+ pca9698_set_value(0x20, 26, state ? 0 : 1);
+}
+
+void mpc8308_setup_hw(void)
+{
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+ /*
+ * set "startup-finished"-gpios
+ */
+ setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12)));
+ setbits_be32(&immr->gpio[0].dat, 1 << (31-12));
+}
+
+int mpc8308_get_fpga_done(unsigned fpga)
+{
+ return pca9698_get_value(0x20, 20);
+}
+
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_init(bd_t *bd)
+{
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+ sysconf83xx_t *sysconf = &immr->sysconf;
+
+ /* Enable cache snooping in eSDHC system configuration register */
+ out_be32(&sysconf->sdhccr, 0x02000000);
+
+ return fsl_esdhc_mmc_init(bd);
+}
+#endif
+
+static struct pci_region pcie_regions_0[] = {
+ {
+ .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
+ .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
+ .size = CONFIG_SYS_PCIE1_MEM_SIZE,
+ .flags = PCI_REGION_MEM,
+ },
+ {
+ .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
+ .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
+ .size = CONFIG_SYS_PCIE1_IO_SIZE,
+ .flags = PCI_REGION_IO,
+ },
+};
+
+void pci_init_board(void)
+{
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+ sysconf83xx_t *sysconf = &immr->sysconf;
+ law83xx_t *pcie_law = sysconf->pcielaw;
+ struct pci_region *pcie_reg[] = { pcie_regions_0 };
+
+ fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
+ FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+
+ /* Deassert the resets in the control register */
+ out_be32(&sysconf->pecr1, 0xE0008000);
+ udelay(2000);
+
+ /* Configure PCI Express Local Access Windows */
+ out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
+ out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+ mpc83xx_pcie_init(1, pcie_reg);
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ info->portwidth = FLASH_CFI_16BIT;
+ info->chipwidth = FLASH_CFI_BY16;
+ info->interface = FLASH_CFI_X16;
+ return 1;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+ fdt_fixup_dr_usb(blob, bd);
+ fdt_fixup_esdhc(blob, bd);
+
+ return 0;
+}
+#endif
+
+/*
+ * FPGA MII bitbang implementation
+ */
+
+struct fpga_mii {
+ unsigned fpga;
+ int mdio;
+} fpga_mii[] = {
+ { 0, 1},
+ { 1, 1},
+ { 2, 1},
+ { 3, 1},
+};
+
+static int mii_dummy_init(struct bb_miiphy_bus *bus)
+{
+ return 0;
+}
+
+static int mii_mdio_active(struct bb_miiphy_bus *bus)
+{
+ struct fpga_mii *fpga_mii = bus->priv;
+
+ if (fpga_mii->mdio)
+ FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
+ else
+ FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
+
+ return 0;
+}
+
+static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
+{
+ struct fpga_mii *fpga_mii = bus->priv;
+
+ FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
+
+ return 0;
+}
+
+static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
+{
+ struct fpga_mii *fpga_mii = bus->priv;
+
+ if (v)
+ FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
+ else
+ FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
+
+ fpga_mii->mdio = v;
+
+ return 0;
+}
+
+static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
+{
+ u16 gpio;
+ struct fpga_mii *fpga_mii = bus->priv;
+
+ FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
+
+ *v = ((gpio & GPIO_MDIO) != 0);
+
+ return 0;
+}
+
+static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
+{
+ struct fpga_mii *fpga_mii = bus->priv;
+
+ if (v)
+ FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
+ else
+ FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
+
+ return 0;
+}
+
+static int mii_delay(struct bb_miiphy_bus *bus)
+{
+ udelay(1);
+
+ return 0;
+}
+
+struct bb_miiphy_bus bb_miiphy_buses[] = {
+ {
+ .name = "board0",
+ .init = mii_dummy_init,
+ .mdio_active = mii_mdio_active,
+ .mdio_tristate = mii_mdio_tristate,
+ .set_mdio = mii_set_mdio,
+ .get_mdio = mii_get_mdio,
+ .set_mdc = mii_set_mdc,
+ .delay = mii_delay,
+ .priv = &fpga_mii[0],
+ },
+ {
+ .name = "board1",
+ .init = mii_dummy_init,
+ .mdio_active = mii_mdio_active,
+ .mdio_tristate = mii_mdio_tristate,
+ .set_mdio = mii_set_mdio,
+ .get_mdio = mii_get_mdio,
+ .set_mdc = mii_set_mdc,
+ .delay = mii_delay,
+ .priv = &fpga_mii[1],
+ },
+ {
+ .name = "board2",
+ .init = mii_dummy_init,
+ .mdio_active = mii_mdio_active,
+ .mdio_tristate = mii_mdio_tristate,
+ .set_mdio = mii_set_mdio,
+ .get_mdio = mii_get_mdio,
+ .set_mdc = mii_set_mdc,
+ .delay = mii_delay,
+ .priv = &fpga_mii[2],
+ },
+ {
+ .name = "board3",
+ .init = mii_dummy_init,
+ .mdio_active = mii_mdio_active,
+ .mdio_tristate = mii_mdio_tristate,
+ .set_mdio = mii_set_mdio,
+ .get_mdio = mii_get_mdio,
+ .set_mdc = mii_set_mdc,
+ .delay = mii_delay,
+ .priv = &fpga_mii[3],
+ },
+};
+
+int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
+ sizeof(bb_miiphy_buses[0]);