diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c
index 5cdee9f..ee93e8b 100644
--- a/board/freescale/p1022ds/p1022ds.c
+++ b/board/freescale/p1022ds/p1022ds.c
@@ -27,6 +27,7 @@
 #include <asm/mp.h>
 #include <netdev.h>
 #include <i2c.h>
+#include <hwconfig.h>
 
 #include "../common/ngpixis.h"
 
@@ -90,34 +91,58 @@
 
 #define CONFIG_TFP410_I2C_ADDR	0x38
 
+/* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */
+#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK	0x0c
+#define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK	0x03
+
+/* Route the I2C1 pins to the SSI port instead. */
+#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI	0x08
+
+/* Choose the 12.288Mhz codec reference clock */
+#define CONFIG_PIXIS_BRDCFG1_AUDCLK_12		0x02
+
+/* Choose the 11.2896Mhz codec reference clock */
+#define CONFIG_PIXIS_BRDCFG1_AUDCLK_11		0x01
+
 int misc_init_r(void)
 {
 	u8 temp;
+	const char *audclk;
+	size_t arglen;
 
-	/*  Enable the TFP410 Encoder */
+	/* For DVI, enable the TFP410 Encoder. */
 
 	temp = 0xBF;
 	if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
 		return -1;
-
-	/* Verify if enabled */
-	temp = 0;
 	if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
 		return -1;
-
 	debug("DVI Encoder Read: 0x%02x\n", temp);
 
 	temp = 0x10;
 	if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
 		return -1;
-
-	/* Verify if enabled */
-	temp = 0;
 	if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
 		return -1;
-
 	debug("DVI Encoder Read: 0x%02x\n",temp);
 
+	/*
+	 * Enable the reference clock for the WM8776 codec, and route the MUX
+	 * pins for SSI. The default is the 12.288 MHz clock
+	 */
+
+	temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK |
+		CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK);
+	temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI;
+
+	audclk = hwconfig_arg("audclk", &arglen);
+	/* Check the first two chars only */
+	if (audclk && (strncmp(audclk, "11", 2) == 0))
+		temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11;
+	else
+		temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12;
+	out_8(&pixis->brdcfg1, temp);
+
 	return 0;
 }
 
@@ -310,6 +335,27 @@
 }
 
 #ifdef CONFIG_OF_BOARD_SETUP
+/**
+ * ft_codec_setup - fix up the clock-frequency property of the codec node
+ *
+ * Update the clock-frequency property based on the value of the 'audclk'
+ * hwconfig option.  If audclk is not specified, then default to 12.288MHz.
+ */
+static void ft_codec_setup(void *blob, const char *compatible)
+{
+	const char *audclk;
+	size_t arglen;
+	u32 freq;
+
+	audclk = hwconfig_arg("audclk", &arglen);
+	if (audclk && (strncmp(audclk, "11", 2) == 0))
+		freq = 11289600;
+	else
+		freq = 12288000;
+
+	do_fixup_by_compat_u32(blob, compatible, "clock-frequency", freq, 1);
+}
+
 void ft_board_setup(void *blob, bd_t *bd)
 {
 	phys_addr_t base;
@@ -327,6 +373,9 @@
 #ifdef CONFIG_FSL_SGMII_RISER
 	fsl_sgmii_riser_fdt_fixup(blob);
 #endif
+
+	/* Update the WM8776 node's clock frequency property */
+	ft_codec_setup(blob, "wlf,wm8776");
 }
 #endif