diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index c33a12a..a1be735 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1772,7 +1772,7 @@
  */
 static int
 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
-(uint32_t write_group, uint32_t read_group, uint32_t test_bgn)
+(const u32 rw_group, const u32 test_bgn)
 {
 	/* We start at zero, so have one less dq to devide among */
 	const u32 delay_step = IO_IO_IN_DELAY_MAX /
@@ -1780,8 +1780,7 @@
 	int found;
 	u32 i, p, d, r;
 
-	debug("%s:%d (%u,%u,%u)\n", __func__, __LINE__,
-	      write_group, read_group, test_bgn);
+	debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn);
 
 	/* Try different dq_in_delays since the DQ path is shorter than DQS. */
 	for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
@@ -1790,9 +1789,8 @@
 		     i < RW_MGR_MEM_DQ_PER_READ_DQS;
 		     i++, p++, d += delay_step) {
 			debug_cond(DLEVEL == 1,
-				   "%s:%d: g=%u/%u r=%u i=%u p=%u d=%u\n",
-				   __func__, __LINE__, write_group, read_group,
-				   r, i, p, d);
+				   "%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
+				   __func__, __LINE__, rw_group, r, i, p, d);
 
 			scc_mgr_set_dq_in_delay(p, d);
 			scc_mgr_load_dq(p);
@@ -1801,11 +1799,11 @@
 		writel(0, &sdr_scc_mgr->update);
 	}
 
-	found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(read_group);
+	found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group);
 
 	debug_cond(DLEVEL == 1,
-		   "%s:%d: g=%u/%u found=%u; Reseting delay chain to zero\n",
-		   __func__, __LINE__, write_group, read_group, found);
+		   "%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
+		   __func__, __LINE__, rw_group, found);
 
 	for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 	     r += NUM_RANKS_PER_SHADOW_REG) {
@@ -2259,7 +2257,7 @@
 	 * DQS and DQS Eanble Signal Relationships.
 	 */
 	ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay(
-						rw_group, rw_group, test_bgn);
+						rw_group, test_bgn);
 	return ret;
 }