tree 9d2ee4b001275fe6a2191ead6ec3913e033a783d
parent 3aba25bc382beeb8a92b46d23fd1db47dfcb1121
author Michal Simek <michal.simek@xilinx.com> 1612880895 +0100
committer Michal Simek <michal.simek@xilinx.com> 1614088619 +0100

clk: zynq: Add dummy clock enable function

A lot of Xilinx drivers are checking -ENOSYS which means that clock driver
doesn't have enable function. Remove this checking from drivers and create
dummy enable function as was done for clk_fixed_rate driver by
commit 6bf6d81c1112 ("clk: fixed_rate: add dummy enable() function").

Signed-off-by: Michal Simek <michal.simek@xilinx.com>