powerpc/85xx: add support for FM2 DTSEC5

Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second
Fman, so add the Fman and SerDes macros for that DTSEC.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 4b52dad..8aac1de 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -68,6 +68,7 @@
 	[SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
 	[SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
 	[SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
+	[SGMII_FM2_DTSEC5] = "SGMII_FM2_DTSEC5",
 	[XAUI_FM1] = "XAUI_FM1",
 	[XAUI_FM2] = "XAUI_FM2",
 	[AURORA] = "DEBUG",
@@ -658,6 +659,7 @@
 		case SGMII_FM2_DTSEC2:
 		case SGMII_FM2_DTSEC3:
 		case SGMII_FM2_DTSEC4:
+		case SGMII_FM2_DTSEC5:
 		case XAUI_FM1:
 		case XAUI_FM2:
 		case SRIO1:
@@ -717,6 +719,10 @@
 			serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
 					    FSL_CORENET_DEVDISR2_DTSEC2_4;
 			break;
+		case SGMII_FM2_DTSEC5:
+			serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
+					    FSL_CORENET_DEVDISR2_DTSEC2_5;
+			break;
 		case XAUI_FM1:
 			serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1	|
 					    FSL_CORENET_DEVDISR2_10GEC1;
diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h
index 0f31af1..22525f1 100644
--- a/arch/powerpc/include/asm/fsl_serdes.h
+++ b/arch/powerpc/include/asm/fsl_serdes.h
@@ -41,6 +41,7 @@
 	SGMII_FM2_DTSEC2,
 	SGMII_FM2_DTSEC3,
 	SGMII_FM2_DTSEC4,
+	SGMII_FM2_DTSEC5,
 	SGMII_TSEC1,
 	SGMII_TSEC2,
 	SGMII_TSEC3,
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 83f8813..9bdfd97 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1729,6 +1729,7 @@
 #define FSL_CORENET_DEVDISR2_DTSEC2_2	0x00004000
 #define FSL_CORENET_DEVDISR2_DTSEC2_3	0x00002000
 #define FSL_CORENET_DEVDISR2_DTSEC2_4	0x00001000
+#define FSL_CORENET_DEVDISR2_DTSEC2_5	0x00000800
 #define FSL_CORENET_NUM_DEVDISR		2
 	u8	res7[8];
 	u32	powmgtcsr;	/* Power management status & control */
diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index 953c359..9834cd9 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -50,6 +50,9 @@
 #if (CONFIG_SYS_NUM_FM2_DTSEC >= 4)
 	FM_DTSEC_INFO_INITIALIZER(2, 4),
 #endif
+#if (CONFIG_SYS_NUM_FM2_DTSEC >= 5)
+	FM_DTSEC_INFO_INITIALIZER(2, 5),
+#endif
 #if (CONFIG_SYS_NUM_FM1_10GEC >= 1)
 	FM_TGEC_INFO_INITIALIZER(1, 1),
 #endif
diff --git a/include/fm_eth.h b/include/fm_eth.h
index c7c6882..05121ea 100644
--- a/include/fm_eth.h
+++ b/include/fm_eth.h
@@ -35,6 +35,7 @@
 	FM2_DTSEC2,
 	FM2_DTSEC3,
 	FM2_DTSEC4,
+	FM2_DTSEC5,
 	FM2_10GEC1,
 	NUM_FM_PORTS,
 };