tree fd36d56ba6c9e344287fa52d73134b8c6842d83c
parent a93feb2edc60b9db76ec794bff5ad0fcb10ce3eb
author Patrice Chotard <patrice.chotard@st.com> 1516381360 +0100
committer Tom Rini <trini@konsulko.com> 1517150355 -0500

clk: clk_stm32f: Fix PLLSAICFGR_PLLSAIP_4 divider value

PLLSAIP divider uses 2 bits (bits 16 and 17) into RCC_PLLSAICFGR
register, available combination are :
  00: PLLSAIP = 2
  01: PLLSAIP = 4
  10: PLLSAIP = 6
  11: PLLSAIP = 8

Previously, the divider value was incorrectly set to 6.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>