| commit | 9850d4e52f7f8da1bab7fae32f90e8eba7b4f6af | [log] [tgz] |
|---|---|---|
| author | Tero Kristo <t-kristo@ti.com> | Fri Sep 27 19:14:28 2019 +0300 |
| committer | Tom Rini <trini@konsulko.com> | Fri Oct 11 13:32:39 2019 -0400 |
| tree | eda030a2d6c8602a85030b59d91d9a8ad803aaa0 | |
| parent | e8e683d33b0ccd43e03809bf4ea88a899a867473 [diff] |
board: ti: am43xx-idk: Configure the CDCE913 clock synthesizer AM43xx-IDK boards contain the CDCE913 clock synthesizer, and their reset crystal capacitance load value of 10pF is wrong leading into lost packets in certain networking tests. Add DT data for this device, and probe it from the board file to program the crystal capacitance load value to 0pF to avoid any problems. Signed-off-by: Tero Kristo <t-kristo@ti.com>