commit 97405d843ece2a53e67b801e02ee42005d26e172
author Lokesh Vutla <lokeshvutla@ti.com> Thu May 30 03:19:38 2013 +0000
committer Tom Rini <trini@ti.com> Mon Jun 10 08:43:10 2013 -0400
tree 13c4b866c44ebbbb7033f7490921fcb6dffa6004
parent 7f36c88f64ee1affd4db78b2c2f4a616abceb84c

ARM: DRA7xx: clocks: Update PLL values

Update PLL values.
SYS_CLKSEL value for 20MHz is changed to 2. In other platforms
SYS_CLKSEL value 2 represents reserved. But in sys_clk array
ind 1 is used for 13Mhz. Since other platforms are not using
13Mhz, reusing index 1 for 20MHz.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>

include/configs/dra7xx_evm.h

diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 35dec08..0eea28c 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -39,4 +39,6 @@
 #define CONFIG_CONS_INDEX		1
 #define CONFIG_SYS_NS16550_COM1		UART1_BASE
 #define CONFIG_BAUDRATE			115200
+
+#define CONFIG_SYS_OMAP_ABE_SYSCK
 #endif /* __CONFIG_DRA7XX_EVM_H */