tree c2f1b8a2cf17dcc568c546ec58d1a7030b8e7351
parent 0d61f8e5f1c0035c3ee105d940b5b8d90bcec5b0
author Chris Morgan <macromorgan@hotmail.com> 1676327259 -0600
committer Kever Yang <kever.yang@rock-chips.com> 1677578847 +0800

rockchip: rk3568: enable automatic power savings

It enables automatic clock gating on idle, disables the eDP phy by
default, and sets the core pvtpll ring length. It is reported this
lowers the temperature on at least one SoC by 7C.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>