tree c8be22adb9f0fbdcc7a8d4e0f5c6e97d8f8047f1
parent 66103759595b1db6fb7355f95eca8af2334c4749
author Neha Malcom Francis <n-francis@ti.com> 1716889794 +0530
committer Tom Rini <trini@konsulko.com> 1718317757 -0600

arm: dts: k3-j721s2-r5: Change GTC clock parent

MAIN_PLL0 has a flag set in DM (Device Manager) that removes its
capability to re-initialise clock frequencies. A72 CPU clock (GTC) and
RGMII has MAIN_PLL3 as their parent which does not have this flag. While
RGMII needs re-initialization to default frequency to be able to get
250MHz with its divider, GTC can not get its required 200MHz with its
dividers. Thus move GTC clock parent on J721S2 from MAIN_PLL3_HSDIV1 to
MAIN_PLL0_HSDIV6. This was already done on CPTS node in kernel which was
similarly affected (linked).

Link: https://lore.kernel.org/all/20230605110443.84568-1-n-francis@ti.com/
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>