| commit | 9293d7fd502ce29302fadb8b4ccb9231ec0bcc66 | [log] [tgz] |
|---|---|---|
| author | Ye.Li <B37916@freescale.com> | Tue Sep 09 10:17:00 2014 +0800 |
| committer | Stefano Babic <sbabic@denx.de> | Mon Sep 29 10:24:07 2014 +0200 |
| tree | fd8ef54e242e4c0a0607f86045a2e6c893a4728a | |
| parent | adca1875c8090dea9b163550d8607ccba5418819 [diff] |
imx: mx6: Checking PLL2 PFD0 and PFD2 for periph_clk before PFD reset Checking the pre_periph_clk_sel and pre_periph2_clk of CCM CBCMR register, if the PLL2 PFD0 or PLL2 PFD2 is used for the clock source, do not reset this PFD to avoid system hang. Customers may set this in DDR script or use BT_FREQ to select low freq boot. Signed-off-by: Ye.Li <B37916@freescale.com>