net: sh_eth: add support for SH7757's ETHER
SH7757 has ETHER and GETHER. This patch supports EHTER only.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 53d918d..17dd0d2 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -277,6 +277,7 @@
static int sh_eth_reset(struct sh_eth_dev *eth)
{
int port = eth->port;
+#if defined(CONFIG_CPU_SH7763)
int ret = 0, i;
/* Start e-dmac transmitter and receiver */
@@ -296,6 +297,13 @@
}
return ret;
+#else
+ outl(inl(EDMR(port)) | EDMR_SRST, EDMR(port));
+ udelay(3000);
+ outl(inl(EDMR(port)) & ~EDMR_SRST, EDMR(port));
+
+ return 0;
+#endif
}
static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
@@ -339,9 +347,11 @@
/* Point the controller to the tx descriptor list. Must use physical
addresses */
outl(ADDR_TO_PHY(port_info->tx_desc_base), TDLAR(port));
+#if defined(CONFIG_CPU_SH7763)
outl(ADDR_TO_PHY(port_info->tx_desc_base), TDFAR(port));
outl(ADDR_TO_PHY(cur_tx_desc), TDFXR(port));
outl(0x01, TDFFR(port));/* Last discriptor bit */
+#endif
err:
return ret;
@@ -405,9 +415,11 @@
/* Point the controller to the rx descriptor list */
outl(ADDR_TO_PHY(port_info->rx_desc_base), RDLAR(port));
+#if defined(CONFIG_CPU_SH7763)
outl(ADDR_TO_PHY(port_info->rx_desc_base), RDFAR(port));
outl(ADDR_TO_PHY(cur_rx_desc), RDFXR(port));
outl(RDFFR_RDLF, RDFFR(port));
+#endif
return ret;
@@ -532,11 +544,18 @@
outl(0, TFTR(port));
outl((FIFO_SIZE_T | FIFO_SIZE_R), FDR(port));
outl(RMCR_RST, RMCR(port));
+#ifndef CONFIG_CPU_SH7757
outl(0, RPADIR(port));
+#endif
outl((FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR(port));
/* Configure e-mac registers */
+#if defined(CONFIG_CPU_SH7757)
+ outl(ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP |
+ ECSIPR_MPDIP | ECSIPR_ICDIP, ECSIPR(port));
+#else
outl(0, ECSIPR(port));
+#endif
/* Set Mac address */
val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 |
@@ -547,11 +566,16 @@
outl(val, MALR(port));
outl(RFLR_RFL_MIN, RFLR(port));
+#ifndef CONFIG_CPU_SH7757
outl(0, PIPR(port));
+#endif
outl(APR_AP, APR(port));
outl(MPR_MP, MPR(port));
+#ifdef CONFIG_CPU_SH7757
+ outl(TPAUSER_UNLIMITED, TPAUSER(port));
+#else
outl(TPAUSER_TPAUSE, TPAUSER(port));
-
+#endif
/* Configure phy */
ret = sh_eth_phy_config(eth);
if (ret) {
@@ -562,6 +586,7 @@
phy_status = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, 1);
/* Set the transfer speed */
+#ifdef CONFIG_CPU_SH7763
if (phy_status & (PHY_S_100X_F|PHY_S_100X_H)) {
printf(SHETHER_NAME ": 100Base/");
outl(GECMR_100B, GECMR(port));
@@ -569,6 +594,16 @@
printf(SHETHER_NAME ": 10Base/");
outl(GECMR_10B, GECMR(port));
}
+#endif
+#if defined(CONFIG_CPU_SH7757)
+ if (phy_status & (PHY_S_100X_F|PHY_S_100X_H)) {
+ printf("100Base/");
+ outl(1, RTRATE(port));
+ } else {
+ printf("10Base/");
+ outl(0, RTRATE(port));
+ }
+#endif
/* Check if full duplex mode is supported by the phy */
if (phy_status & (PHY_S_100X_F|PHY_S_10T_F)) {