ppc4xx: Change LWMON5 to not use OCM for init-ram and POST anymore
This patch configures the LWMON5 port to use d-cache as init-ram and
the unused GPT0_COMP6 as POST WORD storage.
Signed-off-by: Stefan Roese <sr@denx.de>
diff --git a/board/lwmon5/init.S b/board/lwmon5/init.S
index 6798e80..5aade72 100644
--- a/board/lwmon5/init.S
+++ b/board/lwmon5/init.S
@@ -57,7 +57,7 @@
#ifdef CFG_INIT_RAM_DCACHE
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry(CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
+ tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
#endif
/* TLB-entry for PCI Memory */
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index 5210024..0bf536b 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -71,15 +71,20 @@
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer
*----------------------------------------------------------------------*/
-/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
-#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
-#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
-
+/*
+ * On LWMON5 we use D-cache as init-ram and stack pointer. We also move
+ * the POST_WORD from OCM to a 440EPx register that preserves it's
+ * content during reset (GPT0_COM6). This way we reserve the OCM (16k)
+ * for logbuffer only.
+ */
+#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */
+#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
#define CFG_INIT_RAM_END (4 << 10)
-#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
-#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+#define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6)
+ /* unused GPT0 COMP reg */
/*-----------------------------------------------------------------------
* Serial Port
diff --git a/include/ppc440.h b/include/ppc440.h
index 90e56b0..b0d16fb 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -1354,8 +1354,6 @@
#define plb1_bearl (PLB_ARBITER_BASE+ 0x0C)
#define plb1_bearh (PLB_ARBITER_BASE+ 0x0D)
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
/* Pin Function Control Register 1 */
#define SDR0_PFC1 0x4101
#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
@@ -1421,7 +1419,7 @@
#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
-#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
+#define GPT0_COMP6 0x00000098
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define SDR0_USB2D0CR 0x0320