miiphy: convert to linux/mii.h
The include/miiphy.h header duplicates a lot of things from linux/mii.h.
So punt all the things that overlap to keep the API simple and to make
merging between U-Boot and Linux simpler.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
diff --git a/drivers/net/4xx_enet.c b/drivers/net/4xx_enet.c
index 45ff4f3..b1763b1 100644
--- a/drivers/net/4xx_enet.c
+++ b/drivers/net/4xx_enet.c
@@ -1185,16 +1185,16 @@
}
#endif /* defined(CONFIG_PHY_RESET) */
- miiphy_read (dev->name, reg, PHY_BMSR, ®_short);
+ miiphy_read (dev->name, reg, MII_BMSR, ®_short);
/*
* Wait if PHY is capable of autonegotiation and autonegotiation is not complete
*/
- if ((reg_short & PHY_BMSR_AUTN_ABLE)
- && !(reg_short & PHY_BMSR_AUTN_COMP)) {
+ if ((reg_short & BMSR_ANEGCAPABLE)
+ && !(reg_short & BMSR_ANEGCOMPLETE)) {
puts ("Waiting for PHY auto negotiation to complete");
i = 0;
- while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
+ while (!(reg_short & BMSR_ANEGCOMPLETE)) {
/*
* Timeout reached ?
*/
@@ -1207,7 +1207,7 @@
putc ('.');
}
udelay (1000); /* 1 ms */
- miiphy_read (dev->name, reg, PHY_BMSR, ®_short);
+ miiphy_read (dev->name, reg, MII_BMSR, ®_short);
}
puts (" done\n");
udelay (500000); /* another 500 ms (results in faster booting) */
diff --git a/drivers/net/altera_tse.c b/drivers/net/altera_tse.c
index d45aab1..54a944b 100644
--- a/drivers/net/altera_tse.c
+++ b/drivers/net/altera_tse.c
@@ -475,12 +475,12 @@
*/
mii_reg = tse_mdio_read(priv, MIIM_STATUS);
- if (!(mii_reg & MIIM_STATUS_LINK) && (mii_reg & PHY_BMSR_AUTN_ABLE)
- && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
+ if (!(mii_reg & MIIM_STATUS_LINK) && (mii_reg & BMSR_ANEGCAPABLE)
+ && !(mii_reg & BMSR_ANEGCOMPLETE)) {
int i = 0;
puts("Waiting for PHY auto negotiation to complete");
- while (!(mii_reg & PHY_BMSR_AUTN_COMP)) {
+ while (!(mii_reg & BMSR_ANEGCOMPLETE)) {
/*
* Timeout reached ?
*/
@@ -643,13 +643,13 @@
"Unknown/Generic PHY",
32,
(struct phy_cmd[]){ /* config */
- {PHY_BMCR, PHY_BMCR_RESET, NULL},
- {PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG, NULL},
+ {MII_BMCR, BMCR_RESET, NULL},
+ {MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART, NULL},
{miim_end,}
},
(struct phy_cmd[]){ /* startup */
- {PHY_BMSR, miim_read, NULL},
- {PHY_BMSR, miim_read, &mii_parse_sr},
+ {MII_BMSR, miim_read, NULL},
+ {MII_BMSR, miim_read, &mii_parse_sr},
{miim_end,}
},
(struct phy_cmd[]){ /* shutdown */
diff --git a/drivers/net/altera_tse.h b/drivers/net/altera_tse.h
index c1cb79e..8880bfc 100644
--- a/drivers/net/altera_tse.h
+++ b/drivers/net/altera_tse.h
@@ -41,8 +41,6 @@
#define MIIM_STATUS 0x1
#define MIIM_STATUS_AN_DONE 0x00000020
#define MIIM_STATUS_LINK 0x0004
-#define PHY_BMSR_AUTN_ABLE 0x0008
-#define PHY_BMSR_AUTN_COMP 0x0020
#define MIIM_PHYIR1 0x2
#define MIIM_PHYIR2 0x3
diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c
index 43a3d79..56cd2aa 100644
--- a/drivers/net/davinci_emac.c
+++ b/drivers/net/davinci_emac.c
@@ -236,7 +236,7 @@
{
u_int16_t dummy;
- return(davinci_eth_phy_read(phy_addr, PHY_PHYIDR1, &dummy));
+ return(davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy));
}
static int gen_get_link_speed(int phy_addr)
@@ -280,19 +280,19 @@
{
u_int16_t tmp;
- if (!davinci_eth_phy_read(phy_addr, PHY_BMCR, &tmp))
+ if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
return(0);
/* Restart Auto_negotiation */
- tmp |= PHY_BMCR_AUTON;
- davinci_eth_phy_write(phy_addr, PHY_BMCR, tmp);
+ tmp |= BMCR_ANENABLE;
+ davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
/*check AutoNegotiate complete */
udelay (10000);
- if (!davinci_eth_phy_read(phy_addr, PHY_BMSR, &tmp))
+ if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
return(0);
- if (!(tmp & PHY_BMSR_AUTN_COMP))
+ if (!(tmp & BMSR_ANEGCOMPLETE))
return(0);
return(gen_get_link_speed(phy_addr));
@@ -694,14 +694,14 @@
return(0);
/* Get PHY ID and initialize phy_ops for a detected PHY */
- if (!davinci_eth_phy_read(active_phy_addr, PHY_PHYIDR1, &tmp)) {
+ if (!davinci_eth_phy_read(active_phy_addr, MII_PHYSID1, &tmp)) {
active_phy_addr = 0xff;
return(0);
}
phy_id = (tmp << 16) & 0xffff0000;
- if (!davinci_eth_phy_read(active_phy_addr, PHY_PHYIDR2, &tmp)) {
+ if (!davinci_eth_phy_read(active_phy_addr, MII_PHYSID2, &tmp)) {
active_phy_addr = 0xff;
return(0);
}
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 2f923f2..3f5eeb7 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -318,19 +318,19 @@
u16 ctrl, oldctrl;
do {
- eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl);
- oldctrl = ctrl & PHY_BMCR_AUTON;
+ eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
+ oldctrl = ctrl & BMCR_ANENABLE;
- ctrl ^= PHY_BMCR_AUTON;
- eth_mdio_write(dev, phy_addr, PHY_BMCR, ctrl);
- eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl);
- ctrl &= PHY_BMCR_AUTON;
+ ctrl ^= BMCR_ANENABLE;
+ eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl);
+ eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
+ ctrl &= BMCR_ANENABLE;
if (ctrl == oldctrl) {
phy_addr++;
} else {
- ctrl ^= PHY_BMCR_AUTON;
- eth_mdio_write(dev, phy_addr, PHY_BMCR, ctrl);
+ ctrl ^= BMCR_ANENABLE;
+ eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl);
return phy_addr;
}
@@ -347,10 +347,10 @@
int timeout = CONFIG_PHYRESET_TIMEOUT;
u32 phy_addr = priv->address;
- eth_mdio_write(dev, phy_addr, PHY_BMCR, PHY_BMCR_RESET);
+ eth_mdio_write(dev, phy_addr, MII_BMCR, BMCR_RESET);
do {
- eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl);
- if (!(ctrl & PHY_BMCR_RESET))
+ eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
+ if (!(ctrl & BMCR_RESET))
break;
udelay(1000);
} while (timeout--);
@@ -386,33 +386,33 @@
return -1;
#if defined(CONFIG_DW_AUTONEG)
- bmcr = PHY_BMCR_AUTON | PHY_BMCR_RST_NEG | PHY_BMCR_100MB | \
- PHY_BMCR_DPLX | PHY_BMCR_1000_MBPS;
+ bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_SPEED100 | \
+ BMCR_FULLDPLX | BMCR_SPEED1000;
#else
- bmcr = PHY_BMCR_100MB | PHY_BMCR_DPLX;
+ bmcr = BMCR_SPEED100 | BMCR_FULLDPLX;
#if defined(CONFIG_DW_SPEED10M)
- bmcr &= ~PHY_BMCR_100MB;
+ bmcr &= ~BMCR_SPEED100;
#endif
#if defined(CONFIG_DW_DUPLEXHALF)
- bmcr &= ~PHY_BMCR_DPLX;
+ bmcr &= ~BMCR_FULLDPLX;
#endif
#endif
- if (eth_mdio_write(dev, phy_addr, PHY_BMCR, bmcr) < 0)
+ if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0)
return -1;
/* Read the phy status register and populate priv structure */
#if defined(CONFIG_DW_AUTONEG)
timeout = CONFIG_AUTONEG_TIMEOUT;
do {
- eth_mdio_read(dev, phy_addr, PHY_BMSR, &bmsr);
- if (bmsr & PHY_BMSR_AUTN_COMP)
+ eth_mdio_read(dev, phy_addr, MII_BMSR, &bmsr);
+ if (bmsr & BMSR_ANEGCOMPLETE)
break;
udelay(1000);
} while (timeout--);
- eth_mdio_read(dev, phy_addr, PHY_ANLPAR, &anlpar);
- eth_mdio_read(dev, phy_addr, PHY_1000BTSR, &btsr);
+ eth_mdio_read(dev, phy_addr, MII_LPA, &anlpar);
+ eth_mdio_read(dev, phy_addr, MII_STAT1000, &btsr);
if (btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) {
priv->speed = SPEED_1000M;
@@ -421,28 +421,28 @@
else
priv->duplex = HALF_DUPLEX;
} else {
- if (anlpar & PHY_ANLPAR_100)
+ if (anlpar & LPA_100)
priv->speed = SPEED_100M;
else
priv->speed = SPEED_10M;
- if (anlpar & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD))
+ if (anlpar & (LPA_10FULL | LPA_100FULL))
priv->duplex = FULL_DUPLEX;
else
priv->duplex = HALF_DUPLEX;
}
#else
- if (eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl) < 0)
+ if (eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl) < 0)
return -1;
- if (ctrl & PHY_BMCR_DPLX)
+ if (ctrl & BMCR_FULLDPLX)
priv->duplex = FULL_DUPLEX;
else
priv->duplex = HALF_DUPLEX;
- if (ctrl & PHY_BMCR_1000_MBPS)
+ if (ctrl & BMCR_SPEED1000)
priv->speed = SPEED_1000M;
- else if (ctrl & PHY_BMCR_100_MBPS)
+ else if (ctrl & BMCR_SPEED100)
priv->speed = SPEED_100M;
else
priv->speed = SPEED_10M;
diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c
index ae0e0d4..86709a7 100644
--- a/drivers/net/eepro100.c
+++ b/drivers/net/eepro100.c
@@ -335,7 +335,7 @@
}
/* read id2 register */
- if (get_phyreg(dev, addr, PHY_PHYIDR2, &value) != 0) {
+ if (get_phyreg(dev, addr, MII_PHYSID2, &value) != 0) {
printf("%s: mii read timeout!\n", devname);
return NULL;
}
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 0d0f392..c438962 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -163,20 +163,20 @@
* Reset PHY, then delay 300ns
*/
#ifdef CONFIG_MX27
- miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_MIPGSR, 0x00FF);
+ miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, MII_DCOUNTER, 0x00FF);
#endif
- miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR,
- PHY_BMCR_RESET);
+ miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, MII_BMCR,
+ BMCR_RESET);
udelay(1000);
/*
* Set the auto-negotiation advertisement register bits
*/
- miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_ANAR,
- PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD |
- PHY_ANLPAR_10 | PHY_ANLPAR_PSB_802_3);
- miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR,
- PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+ miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, MII_ADVERTISE,
+ LPA_100FULL | LPA_100HALF | LPA_10FULL |
+ LPA_10HALF | PHY_ANLPAR_PSB_802_3);
+ miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, MII_BMCR,
+ BMCR_ANENABLE | BMCR_ANRESTART);
return 0;
}
@@ -197,12 +197,12 @@
}
if (miiphy_read(dev->name, CONFIG_FEC_MXC_PHYADDR,
- PHY_BMSR, &status)) {
+ MII_BMSR, &status)) {
printf("%s: Autonegotiation failed. status: 0x%04x\n",
dev->name, status);
return -1;
}
- } while (!(status & PHY_BMSR_LS));
+ } while (!(status & BMSR_LSTATUS));
return 0;
}
diff --git a/drivers/net/fsl_mcdmafec.c b/drivers/net/fsl_mcdmafec.c
index 35a6dfb..5330dbc 100644
--- a/drivers/net/fsl_mcdmafec.c
+++ b/drivers/net/fsl_mcdmafec.c
@@ -200,7 +200,7 @@
cbd_t *pTbd, *pUsedTbd;
u16 phyStatus;
- miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus);
+ miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus);
/* process all the consumed TBDs */
while (info->cleanTbdNum < CONFIG_SYS_TX_ETH_BUFFER) {
diff --git a/drivers/net/inca-ip_sw.c b/drivers/net/inca-ip_sw.c
index 492f5ce..bd3360c 100644
--- a/drivers/net/inca-ip_sw.c
+++ b/drivers/net/inca-ip_sw.c
@@ -756,7 +756,7 @@
(0x1 << 31) | /* RA */
(0x0 << 30) | /* Read */
(0x6 << 21) | /* LAN */
- (6 << 16)); /* PHY_ANER */
+ (6 << 16)); /* MII_EXPANSION */
do {
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg6);
} while (phyReg6 & (1 << 31));
@@ -769,7 +769,7 @@
(0x1 << 31) | /* RA */
(0x0 << 30) | /* Read */
(0x6 << 21) | /* LAN */
- (4 << 16)); /* PHY_ANAR */
+ (4 << 16)); /* MII_ADVERTISE */
do {
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg4);
} while (phyReg4 & (1 << 31));
@@ -782,7 +782,7 @@
(0x1 << 31) | /* RA */
(0x0 << 30) | /* Read */
(0x6 << 21) | /* LAN */
- (5 << 16)); /* PHY_ANLPAR */
+ (5 << 16)); /* MII_LPA */
do {
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg5);
} while (phyReg5 & (1 << 31));
diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c
index 64be5de..a08ff27 100644
--- a/drivers/net/mcffec.c
+++ b/drivers/net/mcffec.c
@@ -141,7 +141,7 @@
int j, rc;
u16 phyStatus;
- miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus);
+ miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus);
/* section 16.9.23.3
* Wait for ready
diff --git a/drivers/net/mcfmii.c b/drivers/net/mcfmii.c
index 401182d..f959c00 100644
--- a/drivers/net/mcfmii.c
+++ b/drivers/net/mcfmii.c
@@ -171,7 +171,7 @@
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
- phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
+ phytype = mii_send(mk_mii_read(phyno, MII_PHYSID1));
#ifdef ET_DEBUG
printf("PHY type 0x%x pass %d type\n", phytype, pass);
#endif
@@ -180,7 +180,7 @@
phyaddr = phyno;
phytype <<= 16;
phytype |=
- mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
+ mii_send(mk_mii_read(phyno, MII_PHYSID2));
#ifdef ET_DEBUG
printf("PHY @ 0x%x pass %d\n", phyno, pass);
@@ -256,18 +256,18 @@
status = 0;
i++;
/* Read PHY control register */
- miiphy_read(dev->name, info->phy_addr, PHY_BMCR, &status);
+ miiphy_read(dev->name, info->phy_addr, MII_BMCR, &status);
/* If phy set to autonegotiate, wait for autonegotiation done,
* if phy is not autonegotiating, just wait for link up.
*/
- if ((status & PHY_BMCR_AUTON) == PHY_BMCR_AUTON) {
- linkgood = (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS);
+ if ((status & BMCR_ANENABLE) == BMCR_ANENABLE) {
+ linkgood = (BMSR_ANEGCOMPLETE | BMSR_LSTATUS);
} else {
- linkgood = PHY_BMSR_LS;
+ linkgood = BMSR_LSTATUS;
}
/* Read PHY status register */
- miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &status);
+ miiphy_read(dev->name, info->phy_addr, MII_BMSR, &status);
if ((status & linkgood) == linkgood)
break;
diff --git a/drivers/net/ns7520_eth.c b/drivers/net/ns7520_eth.c
index bfa651b..de82b04 100644
--- a/drivers/net/ns7520_eth.c
+++ b/drivers/net/ns7520_eth.c
@@ -387,8 +387,8 @@
ns7520_mii_get_clock_divisor(nPhyMaxMdioClock);
/* reset PHY */
- ns7520_mii_write(PHY_BMCR, PHY_BMCR_RESET);
- ns7520_mii_write(PHY_BMCR, 0);
+ ns7520_mii_write(MII_BMCR, BMCR_RESET);
+ ns7520_mii_write(MII_BMCR, 0);
udelay(3000); /* [2] p.70 says at least 300us reset recovery time. */
@@ -438,23 +438,23 @@
/* run auto-negotation */
/* define what we are capable of */
- ns7520_mii_write(PHY_ANAR,
- PHY_ANLPAR_TXFD |
- PHY_ANLPAR_TX |
- PHY_ANLPAR_10FD |
- PHY_ANLPAR_10 |
+ ns7520_mii_write(MII_ADVERTISE,
+ LPA_100FULL |
+ LPA_100HALF |
+ LPA_10FULL |
+ LPA_10HALF |
PHY_ANLPAR_PSB_802_3);
/* start auto-negotiation */
- ns7520_mii_write(PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+ ns7520_mii_write(MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
/* wait for completion */
ulStartJiffies = get_timer(0);
while (get_timer(0) < ulStartJiffies + NS7520_MII_NEG_DELAY) {
- uiStatus = ns7520_mii_read(PHY_BMSR);
+ uiStatus = ns7520_mii_read(MII_BMSR);
if ((uiStatus &
- (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)) ==
- (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)) {
+ (BMSR_ANEGCOMPLETE | BMSR_LSTATUS)) ==
+ (BMSR_ANEGCOMPLETE | BMSR_LSTATUS)) {
/* lucky we are, auto-negotiation succeeded */
ns7520_link_print_changed();
ns7520_link_update_egcr();
@@ -515,13 +515,13 @@
DEBUG_FN(DEBUG_LINK);
- uiControl = ns7520_mii_read(PHY_BMCR);
+ uiControl = ns7520_mii_read(MII_BMCR);
- if ((uiControl & PHY_BMCR_AUTON) == PHY_BMCR_AUTON) {
- /* PHY_BMSR_LS is only set on autonegotiation */
- uiStatus = ns7520_mii_read(PHY_BMSR);
+ if ((uiControl & BMCR_ANENABLE) == BMCR_ANENABLE) {
+ /* BMSR_LSTATUS is only set on autonegotiation */
+ uiStatus = ns7520_mii_read(MII_BMSR);
- if (!(uiStatus & PHY_BMSR_LS)) {
+ if (!(uiStatus & BMSR_LSTATUS)) {
printk(KERN_WARNING NS7520_DRIVER_NAME
": link down\n");
/* @TODO Linux: carrier_off */
@@ -582,12 +582,12 @@
DEBUG_FN(DEBUG_MII);
- phyDetected = (PhyType) uiID1 = ns7520_mii_read(PHY_PHYIDR1);
+ phyDetected = (PhyType) uiID1 = ns7520_mii_read(MII_PHYSID1);
switch (phyDetected) {
case PHY_LXT971A:
szName = "LXT971A";
- uiID2 = ns7520_mii_read(PHY_PHYIDR2);
+ uiID2 = ns7520_mii_read(MII_PHYSID2);
nPhyMaxMdioClock = PHY_LXT971_MDIO_MAX_CLK;
cRes = 1;
break;
diff --git a/drivers/net/ns9750_eth.c b/drivers/net/ns9750_eth.c
index d4901b4..9899563 100644
--- a/drivers/net/ns9750_eth.c
+++ b/drivers/net/ns9750_eth.c
@@ -399,8 +399,8 @@
ns9750_mii_get_clock_divisor (nPhyMaxMdioClock);
/* reset PHY */
- ns9750_mii_write(PHY_BMCR, PHY_BMCR_RESET);
- ns9750_mii_write(PHY_BMCR, 0);
+ ns9750_mii_write(MII_BMCR, BMCR_RESET);
+ ns9750_mii_write(MII_BMCR, 0);
/* @TODO check time */
udelay (3000); /* [2] p.70 says at least 300us reset recovery time. But
@@ -455,26 +455,25 @@
DEBUG_FN (DEBUG_LINK);
- uiControl = ns9750_mii_read(PHY_BMCR);
- uiControl &= ~(PHY_BMCR_SPEED_MASK |
- PHY_BMCR_AUTON | PHY_BMCR_DPLX);
+ uiControl = ns9750_mii_read(MII_BMCR);
+ uiControl &= ~(BMCR_SPEED1000 | BMCR_SPEED100 |
+ BMCR_ANENABLE | BMCR_FULLDPLX);
uiLastLinkStatus = 0;
if ((ucLinkMode & FS_EEPROM_AUTONEG_SPEED_MASK) ==
FS_EEPROM_AUTONEG_SPEED_100) {
- uiControl |= PHY_BMCR_100MB;
+ uiControl |= BMCR_SPEED100;
uiLastLinkStatus |= PHY_LXT971_STAT2_100BTX;
- } else
- uiControl |= PHY_BMCR_10_MBPS;
+ }
if ((ucLinkMode & FS_EEPROM_AUTONEG_DUPLEX_MASK) ==
FS_EEPROM_AUTONEG_DUPLEX_FULL) {
- uiControl |= PHY_BMCR_DPLX;
+ uiControl |= BMCR_FULLDPLX;
uiLastLinkStatus |= PHY_LXT971_STAT2_DUPLEX_MODE;
}
- ns9750_mii_write(PHY_BMCR, uiControl);
+ ns9750_mii_write(MII_BMCR, uiControl);
ns9750_link_print_changed ();
ns9750_link_update_egcr ();
@@ -495,23 +494,23 @@
/* run auto-negotation */
/* define what we are capable of */
- ns9750_mii_write(PHY_ANAR,
- PHY_ANLPAR_TXFD |
- PHY_ANLPAR_TX |
- PHY_ANLPAR_10FD |
- PHY_ANLPAR_10 |
+ ns9750_mii_write(MII_ADVERTISE,
+ LPA_100FULL |
+ LPA_100HALF |
+ LPA_10FULL |
+ LPA_10HALF |
PHY_ANLPAR_PSB_802_3);
/* start auto-negotiation */
- ns9750_mii_write(PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+ ns9750_mii_write(MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
/* wait for completion */
ulStartJiffies = get_ticks ();
while (get_ticks () < ulStartJiffies + NS9750_MII_NEG_DELAY) {
- uiStatus = ns9750_mii_read(PHY_BMSR);
+ uiStatus = ns9750_mii_read(MII_BMSR);
if ((uiStatus &
- (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)) ==
- (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)) {
+ (BMSR_ANEGCOMPLETE | BMSR_LSTATUS)) ==
+ (BMSR_ANEGCOMPLETE | BMSR_LSTATUS)) {
/* lucky we are, auto-negotiation succeeded */
ns9750_link_print_changed ();
ns9750_link_update_egcr ();
@@ -569,13 +568,13 @@
DEBUG_FN (DEBUG_LINK);
- uiControl = ns9750_mii_read(PHY_BMCR);
+ uiControl = ns9750_mii_read(MII_BMCR);
- if ((uiControl & PHY_BMCR_AUTON) == PHY_BMCR_AUTON) {
- /* PHY_BMSR_LS is only set on autonegotiation */
- uiStatus = ns9750_mii_read(PHY_BMSR);
+ if ((uiControl & BMCR_ANENABLE) == BMCR_ANENABLE) {
+ /* BMSR_LSTATUS is only set on autonegotiation */
+ uiStatus = ns9750_mii_read(MII_BMSR);
- if (!(uiStatus & PHY_BMSR_LS)) {
+ if (!(uiStatus & BMSR_LSTATUS)) {
printk (KERN_WARNING NS9750_DRIVER_NAME
": link down\n");
/* @TODO Linux: carrier_off */
@@ -634,12 +633,12 @@
DEBUG_FN (DEBUG_MII);
- phyDetected = (PhyType) uiID1 = ns9750_mii_read(PHY_PHYIDR1);
+ phyDetected = (PhyType) uiID1 = ns9750_mii_read(MII_PHYSID1);
switch (phyDetected) {
case PHY_LXT971A:
szName = "LXT971A";
- uiID2 = ns9750_mii_read(PHY_PHYIDR2);
+ uiID2 = ns9750_mii_read(MII_PHYSID2);
nPhyMaxMdioClock = PHY_LXT971_MDIO_MAX_CLK;
cRes = 1;
break;
diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c
index 2d1de02..483a920 100644
--- a/drivers/net/phy/mv88e61xx.c
+++ b/drivers/net/phy/mv88e61xx.c
@@ -354,7 +354,7 @@
printf("Invalid cpu port config, using default port5\n");
}
- RD_PHY(name, MV88E61XX_PRT_OFST, PHY_PHYIDR2, ®);
+ RD_PHY(name, MV88E61XX_PRT_OFST, MII_PHYSID2, ®);
switch (reg &= 0xfff0) {
case 0x1610:
idstr = "88E6161";
diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 3da4c35..aeafeba 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -103,11 +103,11 @@
smc911x_phy_reset(dev);
- smc911x_miiphy_write(dev, 1, PHY_BMCR, PHY_BMCR_RESET);
+ smc911x_miiphy_write(dev, 1, MII_BMCR, BMCR_RESET);
mdelay(1);
- smc911x_miiphy_write(dev, 1, PHY_ANAR, 0x01e1);
- smc911x_miiphy_write(dev, 1, PHY_BMCR, PHY_BMCR_AUTON |
- PHY_BMCR_RST_NEG);
+ smc911x_miiphy_write(dev, 1, MII_ADVERTISE, 0x01e1);
+ smc911x_miiphy_write(dev, 1, MII_BMCR, BMCR_ANENABLE |
+ BMCR_ANRESTART);
timeout = 5000;
do {
@@ -115,9 +115,9 @@
if ((timeout--) == 0)
goto err_out;
- if (smc911x_miiphy_read(dev, 1, PHY_BMSR, &status) != 0)
+ if (smc911x_miiphy_read(dev, 1, MII_BMSR, &status) != 0)
goto err_out;
- } while (!(status & PHY_BMSR_LS));
+ } while (!(status & BMSR_LSTATUS));
printf(DRIVERNAME ": phy initialized\n");
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 77908d1..9c8fe62 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -377,11 +377,11 @@
* (ie - we're capable and it's not done)
*/
mii_reg = read_phy_reg(priv, MIIM_STATUS);
- if ((mii_reg & PHY_BMSR_AUTN_ABLE) && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
+ if ((mii_reg & BMSR_ANEGCAPABLE) && !(mii_reg & BMSR_ANEGCOMPLETE)) {
int i = 0;
puts("Waiting for PHY auto negotiation to complete");
- while (!(mii_reg & PHY_BMSR_AUTN_COMP)) {
+ while (!(mii_reg & BMSR_ANEGCOMPLETE)) {
/*
* Timeout reached ?
*/
@@ -427,17 +427,17 @@
static uint mii_parse_link(uint mii_reg, struct tsec_private *priv)
{
/* We're using autonegotiation */
- if (mii_reg & PHY_BMSR_AUTN_ABLE) {
+ if (mii_reg & BMSR_ANEGCAPABLE) {
uint lpa = 0;
uint gblpa = 0;
/* Check for gigabit capability */
- if (mii_reg & PHY_BMSR_EXT) {
+ if (mii_reg & BMSR_ERCAP) {
/* We want a list of states supported by
* both PHYs in the link
*/
- gblpa = read_phy_reg(priv, PHY_1000BTSR);
- gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2;
+ gblpa = read_phy_reg(priv, MII_STAT1000);
+ gblpa &= read_phy_reg(priv, MII_CTRL1000) << 2;
}
/* Set the baseline so we only have to set them
@@ -457,29 +457,29 @@
return 0;
}
- lpa = read_phy_reg(priv, PHY_ANAR);
- lpa &= read_phy_reg(priv, PHY_ANLPAR);
+ lpa = read_phy_reg(priv, MII_ADVERTISE);
+ lpa &= read_phy_reg(priv, MII_LPA);
- if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) {
+ if (lpa & (LPA_100FULL | LPA_100HALF)) {
priv->speed = 100;
- if (lpa & PHY_ANLPAR_TXFD)
+ if (lpa & LPA_100FULL)
priv->duplexity = 1;
- } else if (lpa & PHY_ANLPAR_10FD)
+ } else if (lpa & LPA_10FULL)
priv->duplexity = 1;
} else {
- uint bmcr = read_phy_reg(priv, PHY_BMCR);
+ uint bmcr = read_phy_reg(priv, MII_BMCR);
priv->speed = 10;
priv->duplexity = 0;
- if (bmcr & PHY_BMCR_DPLX)
+ if (bmcr & BMCR_FULLDPLX)
priv->duplexity = 1;
- if (bmcr & PHY_BMCR_1000_MBPS)
+ if (bmcr & BMCR_SPEED1000)
priv->speed = 1000;
- else if (bmcr & PHY_BMCR_100_MBPS)
+ else if (bmcr & BMCR_SPEED100)
priv->speed = 100;
}
@@ -1645,14 +1645,14 @@
"Micrel KSZ804 PHY",
4,
(struct phy_cmd[]) { /* config */
- {PHY_BMCR, PHY_BMCR_RESET, NULL},
- {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL},
+ {MII_BMCR, BMCR_RESET, NULL},
+ {MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART, NULL},
{miim_end,}
},
(struct phy_cmd[]) { /* startup */
- {PHY_BMSR, miim_read, NULL},
- {PHY_BMSR, miim_read, &mii_parse_sr},
- {PHY_BMSR, miim_read, &mii_parse_link},
+ {MII_BMSR, miim_read, NULL},
+ {MII_BMSR, miim_read, &mii_parse_sr},
+ {MII_BMSR, miim_read, &mii_parse_link},
{miim_end,}
},
(struct phy_cmd[]) { /* shutdown */
@@ -1666,14 +1666,14 @@
"Unknown/Generic PHY",
32,
(struct phy_cmd[]) { /* config */
- {PHY_BMCR, PHY_BMCR_RESET, NULL},
- {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL},
+ {MII_BMCR, BMCR_RESET, NULL},
+ {MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART, NULL},
{miim_end,}
},
(struct phy_cmd[]) { /* startup */
- {PHY_BMSR, miim_read, NULL},
- {PHY_BMSR, miim_read, &mii_parse_sr},
- {PHY_BMSR, miim_read, &mii_parse_link},
+ {MII_BMSR, miim_read, NULL},
+ {MII_BMSR, miim_read, &mii_parse_sr},
+ {MII_BMSR, miim_read, &mii_parse_link},
{miim_end,}
},
(struct phy_cmd[]) { /* shutdown */
diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c
index 35f2368..465a497 100644
--- a/drivers/qe/uec_phy.c
+++ b/drivers/qe/uec_phy.c
@@ -242,7 +242,7 @@
advertise = mii_info->advertising;
/* Setup standard advertisement */
- adv = phy_read (mii_info, PHY_ANAR);
+ adv = phy_read (mii_info, MII_ADVERTISE);
adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
if (advertise & ADVERTISED_10baseT_Half)
adv |= ADVERTISE_10HALF;
@@ -252,7 +252,7 @@
adv |= ADVERTISE_100HALF;
if (advertise & ADVERTISED_100baseT_Full)
adv |= ADVERTISE_100FULL;
- phy_write (mii_info, PHY_ANAR, adv);
+ phy_write (mii_info, MII_ADVERTISE, adv);
}
static void genmii_setup_forced (struct uec_mii_info *mii_info)
@@ -260,24 +260,24 @@
u16 ctrl;
u32 features = mii_info->phyinfo->features;
- ctrl = phy_read (mii_info, PHY_BMCR);
+ ctrl = phy_read (mii_info, MII_BMCR);
- ctrl &= ~(PHY_BMCR_DPLX | PHY_BMCR_100_MBPS |
- PHY_BMCR_1000_MBPS | PHY_BMCR_AUTON);
- ctrl |= PHY_BMCR_RESET;
+ ctrl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 |
+ BMCR_SPEED1000 | BMCR_ANENABLE);
+ ctrl |= BMCR_RESET;
switch (mii_info->speed) {
case SPEED_1000:
if (features & (SUPPORTED_1000baseT_Half
| SUPPORTED_1000baseT_Full)) {
- ctrl |= PHY_BMCR_1000_MBPS;
+ ctrl |= BMCR_SPEED1000;
break;
}
mii_info->speed = SPEED_100;
case SPEED_100:
if (features & (SUPPORTED_100baseT_Half
| SUPPORTED_100baseT_Full)) {
- ctrl |= PHY_BMCR_100_MBPS;
+ ctrl |= BMCR_SPEED100;
break;
}
mii_info->speed = SPEED_10;
@@ -290,7 +290,7 @@
break;
}
- phy_write (mii_info, PHY_BMCR, ctrl);
+ phy_write (mii_info, MII_BMCR, ctrl);
}
/* Enable and Restart Autonegotiation */
@@ -298,9 +298,9 @@
{
u16 ctl;
- ctl = phy_read (mii_info, PHY_BMCR);
- ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
- phy_write (mii_info, PHY_BMCR, ctl);
+ ctl = phy_read (mii_info, MII_BMCR);
+ ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
+ phy_write (mii_info, MII_BMCR, ctl);
}
static int gbit_config_aneg (struct uec_mii_info *mii_info)
@@ -335,7 +335,7 @@
/* The Marvell PHY has an errata which requires
* that certain registers get written in order
* to restart autonegotiation */
- phy_write (mii_info, PHY_BMCR, PHY_BMCR_RESET);
+ phy_write (mii_info, MII_BMCR, BMCR_RESET);
phy_write (mii_info, 0x1d, 0x1f);
phy_write (mii_info, 0x1e, 0x200c);
@@ -373,18 +373,18 @@
u16 status;
/* Status is read once to clear old link state */
- phy_read (mii_info, PHY_BMSR);
+ phy_read (mii_info, MII_BMSR);
/*
* Wait if the link is up, and autonegotiation is in progress
* (ie - we're capable and it's not done)
*/
- status = phy_read(mii_info, PHY_BMSR);
- if ((status & PHY_BMSR_LS) && (status & PHY_BMSR_AUTN_ABLE)
- && !(status & PHY_BMSR_AUTN_COMP)) {
+ status = phy_read(mii_info, MII_BMSR);
+ if ((status & BMSR_LSTATUS) && (status & BMSR_ANEGCAPABLE)
+ && !(status & BMSR_ANEGCOMPLETE)) {
int i = 0;
- while (!(status & PHY_BMSR_AUTN_COMP)) {
+ while (!(status & BMSR_ANEGCOMPLETE)) {
/*
* Timeout reached ?
*/
@@ -395,11 +395,11 @@
i++;
udelay(1000); /* 1 ms */
- status = phy_read(mii_info, PHY_BMSR);
+ status = phy_read(mii_info, MII_BMSR);
}
mii_info->link = 1;
} else {
- if (status & PHY_BMSR_LS)
+ if (status & BMSR_LSTATUS)
mii_info->link = 1;
else
mii_info->link = 0;
@@ -429,13 +429,13 @@
else
mii_info->duplex = DUPLEX_HALF;
} else {
- status = phy_read(mii_info, PHY_ANLPAR);
+ status = phy_read(mii_info, MII_LPA);
- if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD))
+ if (status & (LPA_10FULL | LPA_100FULL))
mii_info->duplex = DUPLEX_FULL;
else
mii_info->duplex = DUPLEX_HALF;
- if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX))
+ if (status & (LPA_100FULL | LPA_100HALF))
mii_info->speed = SPEED_100;
else
mii_info->speed = SPEED_10;
@@ -463,8 +463,8 @@
/* Wait for aneg to complete. */
do
- val = phy_read(mii_info, PHY_BMSR);
- while (--cnt && !(val & PHY_BMSR_AUTN_COMP));
+ val = phy_read(mii_info, MII_BMSR);
+ while (--cnt && !(val & BMSR_ANEGCOMPLETE));
/* Set RDX clk delay. */
phy_write(mii_info, 0x18, 0x7 | (7 << 12));
@@ -511,7 +511,7 @@
temp |= MII_M1111_HWCFG_MODE_RGMII;
phy_write(mii_info, MII_M1111_PHY_EXT_SR, temp);
- phy_write(mii_info, PHY_BMCR, PHY_BMCR_RESET);
+ phy_write(mii_info, MII_BMCR, BMCR_RESET);
}
return 0;
@@ -582,11 +582,11 @@
static int dm9161_init (struct uec_mii_info *mii_info)
{
/* Reset the PHY */
- phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) |
- PHY_BMCR_RESET);
+ phy_write (mii_info, MII_BMCR, phy_read (mii_info, MII_BMCR) |
+ BMCR_RESET);
/* PHY and MAC connect */
- phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) &
- ~PHY_BMCR_ISO);
+ phy_write (mii_info, MII_BMCR, phy_read (mii_info, MII_BMCR) &
+ ~BMCR_ISOLATE);
phy_write (mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT);
@@ -825,11 +825,11 @@
struct phy_info *theInfo = NULL;
/* Grab the bits from PHYIR1, and put them in the upper half */
- phy_reg = phy_read (mii_info, PHY_PHYIDR1);
+ phy_reg = phy_read (mii_info, MII_PHYSID1);
phy_ID = (phy_reg & 0xffff) << 16;
/* Grab the bits from PHYIR2, and put them in the lower half */
- phy_reg = phy_read (mii_info, PHY_PHYIDR2);
+ phy_reg = phy_read (mii_info, MII_PHYSID2);
phy_ID |= (phy_reg & 0xffff);
/* loop through all the known PHY types, and find one that */
@@ -900,8 +900,8 @@
/* handle 88e1111 rev.B2 erratum 5.6 */
if (mii_info->autoneg) {
- status = phy_read (mii_info, PHY_BMCR);
- phy_write (mii_info, PHY_BMCR, status | PHY_BMCR_AUTON);
+ status = phy_read (mii_info, MII_BMCR);
+ phy_write (mii_info, MII_BMCR, status | BMCR_ANENABLE);
}
/* now the B2 will correctly report autoneg completion status */
}
diff --git a/drivers/qe/uec_phy.h b/drivers/qe/uec_phy.h
index 7ac1ff9..929d9bd 100644
--- a/drivers/qe/uec_phy.h
+++ b/drivers/qe/uec_phy.h
@@ -169,24 +169,6 @@
#define ADVERTISED_BNC (1 << 11)
#define ADVERTISED_10000baseT_Full (1 << 12)
-/* Advertisement control register. */
-#define ADVERTISE_SLCT 0x001f /* Selector bits */
-#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
-#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
-#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
-#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
-#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
-#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
-#define ADVERTISE_RESV 0x1c00 /* Unused... */
-#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
-#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
-#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
-
-#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
- ADVERTISE_CSMA)
-#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
- ADVERTISE_100HALF | ADVERTISE_100FULL)
-
/* Taken from mii_if_info and sungem_phy.h */
struct uec_mii_info {
/* Information about the PHY type */