| commit | 8bddf678dbe3c766d4f1c242cda3b9e3ed9e2425 | [log] [tgz] |
|---|---|---|
| author | Chris Packham <judge.packham@gmail.com> | Thu Jan 18 17:16:09 2018 +1300 |
| committer | Stefan Roese <sr@denx.de> | Fri Jan 19 16:30:29 2018 +0100 |
| tree | 79398711daa0e2f0dacbef1b99943e9519fbbaa2 | |
| parent | 2efd27f76ae027deba2a1aaadeece80362ba6297 [diff] |
ddr: marvell: update additional ODT setting The RD_SAMPLE_DELAY field is 5 bits so it needs to be masked with 0x1f instead of 0xf. Rather than checking the read sample delay for all DDR chip selects use the values for the chip selects that are actually configured. Finally continue searching for the max_phase value even if the current read_sample is the same as the max_read_sample. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>