| commit | 8ba595b6bda56eac15d721554ea0ab8fc6a48f73 | [log] [tgz] |
|---|---|---|
| author | Rick Chen <rick@andestech.com> | Thu Nov 14 13:52:25 2019 +0800 |
| committer | Andes <uboot@andestech.com> | Tue Dec 10 08:23:10 2019 +0800 |
| tree | af8b3931b445a7fac6e79195923aa302ab7829a5 | |
| parent | 43a0832ba09068d1ab0628afbe62e498450ece63 [diff] |
riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL The mcache_ctl csr only can be manipulated in M mode. Add SPL_RISCV_MMODE for U-Boot SPL to control cache operation. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Cc: Alan Kao <alankao@andestech.com>