clk: clk_stm32f: Use PLLSAIP as USB 48MHz clock
On all STM32F4 and F7 SoCs family (except STM32F429), PLLSAI
output P can be used as 48MHz clock source for USB and SDMMC.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Tested By: Bruno Herrera <bruherrera@gmail.com>
diff --git a/drivers/misc/stm32_rcc.c b/drivers/misc/stm32_rcc.c
index b436900..dee82c0 100644
--- a/drivers/misc/stm32_rcc.c
+++ b/drivers/misc/stm32_rcc.c
@@ -11,9 +11,14 @@
#include <dm/device-internal.h>
#include <dm/lists.h>
-struct stm32_rcc_clk stm32_rcc_clk_f4 = {
+struct stm32_rcc_clk stm32_rcc_clk_f42x = {
.drv_name = "stm32fx_rcc_clock",
- .soc = STM32F4,
+ .soc = STM32F42X,
+};
+
+struct stm32_rcc_clk stm32_rcc_clk_f469 = {
+ .drv_name = "stm32fx_rcc_clock",
+ .soc = STM32F469,
};
struct stm32_rcc_clk stm32_rcc_clk_f7 = {
@@ -61,7 +66,8 @@
};
static const struct udevice_id stm32_rcc_ids[] = {
- {.compatible = "st,stm32f42xx-rcc", .data = (ulong)&stm32_rcc_clk_f4 },
+ {.compatible = "st,stm32f42xx-rcc", .data = (ulong)&stm32_rcc_clk_f42x },
+ {.compatible = "st,stm32f469-rcc", .data = (ulong)&stm32_rcc_clk_f469 },
{.compatible = "st,stm32f746-rcc", .data = (ulong)&stm32_rcc_clk_f7 },
{.compatible = "st,stm32h743-rcc", .data = (ulong)&stm32_rcc_clk_h7 },
{ }