clk: sandbox: Add sandbox test code for Common Clock Framework [CCF]
This patch provides code to implement the CCF clock tree in sandbox. It
uses all the introduced primitives; some generic ones are reused, some
sandbox specific were developed.
In that way (after introducing the real CCF tree in sandbox) the recently
added to clk-uclass.c: clk_get_by_id() and clk_get_parent_rate() are tested
in their natural work environment.
Usage (sandbox_defconfig and sandbox_flattree_defconfig):
./u-boot --fdt arch/sandbox/dts/test.dtb --command "ut dm clk_ccf"
Signed-off-by: Lukasz Majewski <lukma@denx.de>
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 9c2b284..9399bb7 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -55,7 +55,7 @@
config CLK_CCF
bool "Common Clock Framework [CCF] support "
- depends on CLK_IMX6Q
+ depends on CLK_IMX6Q || SANDBOX_CLK_CCF
help
Enable this option if you want to (re-)use the Linux kernel's Common
Clock Framework [CCF] code in U-Boot's clock driver.
@@ -138,4 +138,12 @@
help
Support for the clock driver of the MPC83xx series of SoCs.
+config SANDBOX_CLK_CCF
+ bool "Sandbox Common Clock Framework [CCF] support "
+ depends on SANDBOX
+ select CLK_CCF
+ help
+ Enable this option if you want to test the Linux kernel's Common
+ Clock Framework [CCF] code in U-Boot's Sandbox clock driver.
+
endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 1a45bf3..37dfd28 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -38,5 +38,6 @@
obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
obj-$(CONFIG_SANDBOX) += clk_sandbox.o
obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
+obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o
obj-$(CONFIG_STM32H7) += clk_stm32h7.o
obj-$(CONFIG_CLK_TI_SCI) += clk-ti-sci.o
diff --git a/drivers/clk/clk_sandbox_ccf.c b/drivers/clk/clk_sandbox_ccf.c
new file mode 100644
index 0000000..edeb0f2
--- /dev/null
+++ b/drivers/clk/clk_sandbox_ccf.c
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * Common Clock Framework [CCF] driver for Sandbox
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <clk.h>
+#include <asm/clk.h>
+#include <clk-uclass.h>
+#include <linux/clk-provider.h>
+#include <sandbox-clk.h>
+
+/*
+ * Sandbox implementation of CCF primitives necessary for clk-uclass testing
+ *
+ * --- Sandbox PLLv3 ---
+ */
+struct clk_pllv3 {
+ struct clk clk;
+ u32 div_mask;
+ u32 div_shift;
+};
+
+static ulong clk_pllv3_get_rate(struct clk *clk)
+{
+ unsigned long parent_rate = clk_get_parent_rate(clk);
+
+ return parent_rate * 24;
+}
+
+static const struct clk_ops clk_pllv3_generic_ops = {
+ .get_rate = clk_pllv3_get_rate,
+};
+
+struct clk *sandbox_clk_pllv3(enum sandbox_pllv3_type type, const char *name,
+ const char *parent_name, void __iomem *base,
+ u32 div_mask)
+{
+ struct clk_pllv3 *pll;
+ struct clk *clk;
+ char *drv_name = "sandbox_clk_pllv3";
+ int ret;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ pll->div_mask = div_mask;
+ clk = &pll->clk;
+
+ ret = clk_register(clk, drv_name, name, parent_name);
+ if (ret) {
+ kfree(pll);
+ return ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
+U_BOOT_DRIVER(sandbox_clk_pll_generic) = {
+ .name = "sandbox_clk_pllv3",
+ .id = UCLASS_CLK,
+ .ops = &clk_pllv3_generic_ops,
+};
+
+/* --- Sandbox PLLv3 --- */
+/* --- Sandbox Gate --- */
+struct clk_gate2 {
+ struct clk clk;
+ bool state;
+};
+
+#define to_clk_gate2(_clk) container_of(_clk, struct clk_gate2, clk)
+
+static int clk_gate2_enable(struct clk *clk)
+{
+ struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
+
+ gate->state = 1;
+ return 0;
+}
+
+static int clk_gate2_disable(struct clk *clk)
+{
+ struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
+
+ gate->state = 0;
+ return 0;
+}
+
+static const struct clk_ops clk_gate2_ops = {
+ .enable = clk_gate2_enable,
+ .disable = clk_gate2_disable,
+ .get_rate = clk_generic_get_rate,
+};
+
+struct clk *sandbox_clk_register_gate2(struct device *dev, const char *name,
+ const char *parent_name,
+ unsigned long flags, void __iomem *reg,
+ u8 bit_idx, u8 cgr_val,
+ u8 clk_gate2_flags)
+{
+ struct clk_gate2 *gate;
+ struct clk *clk;
+ int ret;
+
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate)
+ return ERR_PTR(-ENOMEM);
+
+ gate->state = 0;
+ clk = &gate->clk;
+
+ ret = clk_register(clk, "sandbox_clk_gate2", name, parent_name);
+ if (ret) {
+ kfree(gate);
+ return ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
+U_BOOT_DRIVER(sandbox_clk_gate2) = {
+ .name = "sandbox_clk_gate2",
+ .id = UCLASS_CLK,
+ .ops = &clk_gate2_ops,
+};
+
+/* --- Sandbox Gate --- */
+/* The CCF core driver itself */
+static const struct udevice_id sandbox_clk_ccf_test_ids[] = {
+ { .compatible = "sandbox,clk-ccf" },
+ { }
+};
+
+static const char *const usdhc_sels[] = { "pll3_60m", "pll3_80m", };
+
+static int sandbox_clk_ccf_probe(struct udevice *dev)
+{
+ void *base = NULL;
+ u32 reg;
+
+ clk_dm(SANDBOX_CLK_PLL3,
+ sandbox_clk_pllv3(SANDBOX_PLLV3_USB, "pll3_usb_otg", "osc",
+ base + 0x10, 0x3));
+
+ clk_dm(SANDBOX_CLK_PLL3_60M,
+ sandbox_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8));
+
+ clk_dm(SANDBOX_CLK_PLL3_80M,
+ sandbox_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6));
+
+ /* The HW adds +1 to the divider value (2+1) is the divider */
+ reg = (2 << 19);
+ clk_dm(SANDBOX_CLK_ECSPI_ROOT,
+ sandbox_clk_divider("ecspi_root", "pll3_60m", ®, 19, 6));
+
+ clk_dm(SANDBOX_CLK_ECSPI1,
+ sandbox_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));
+
+ /* Select 'pll3_60m' */
+ reg = 0;
+ clk_dm(SANDBOX_CLK_USDHC1_SEL,
+ sandbox_clk_mux("usdhc1_sel", ®, 16, 1, usdhc_sels,
+ ARRAY_SIZE(usdhc_sels)));
+
+ /* Select 'pll3_80m' */
+ reg = BIT(17);
+ clk_dm(SANDBOX_CLK_USDHC2_SEL,
+ sandbox_clk_mux("usdhc2_sel", ®, 17, 1, usdhc_sels,
+ ARRAY_SIZE(usdhc_sels)));
+
+ return 0;
+}
+
+U_BOOT_DRIVER(sandbox_clk_ccf) = {
+ .name = "sandbox_clk_ccf",
+ .id = UCLASS_CLK,
+ .probe = sandbox_clk_ccf_probe,
+ .of_match = sandbox_clk_ccf_test_ids,
+};