tree c2c32d8381100c8cb890dc904ca496daaf08d3d0
parent 22bfaa1f673ab5442dfb9778eea4c9a18dee42d0
author Loic Poulain <loic.poulain@linaro.org> 1648723177 +0200
committer Stefano Babic <sbabic@denx.de> 1650537863 +0200

imx8ulp: clock: Fix lcd clock algo

The div loop uses reassign and reuse parent_rate, which causes
the parent rate reference to be wrong after the first loop, the
resulting clock becomes incorrect for div != 1.

Fixes: 829e06bf4175 ("imx8ulp: clock: Add MIPI DSI clock and DCNano clock")
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>