diff --git a/include/405gp_enet.h b/include/405gp_enet.h
index 233ea11..b9bdaaf 100644
--- a/include/405gp_enet.h
+++ b/include/405gp_enet.h
@@ -67,7 +67,7 @@
 
 			/*Register addresses */
 #if defined(CONFIG_440)
-#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
 #define ZMII_BASE			(CFG_PERIPHERAL_BASE + 0x0D00)
 #else
 #define ZMII_BASE			(CFG_PERIPHERAL_BASE + 0x0780)
@@ -81,7 +81,7 @@
 #endif /* CONFIG_440 */
 
 #if defined(CONFIG_440)
-#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
 #define EMAC_BASE			    (CFG_PERIPHERAL_BASE + 0x0E00)
 #else
 #define EMAC_BASE			    (CFG_PERIPHERAL_BASE + 0x0800)
diff --git a/include/440_i2c.h b/include/440_i2c.h
index 9fdf7d8..9c90a9e 100644
--- a/include/440_i2c.h
+++ b/include/440_i2c.h
@@ -1,11 +1,11 @@
 #ifndef _440_i2c_h_
 #define _440_i2c_h_
 
-#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
 #define    I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000700)
 #else
 #define    I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000400)
-#endif /*CONFIG_440_EP CONFIG_440_GR*/
+#endif /*CONFIG_440EP CONFIG_440GR*/
 
 #define	   I2C_REGISTERS_BASE_ADDRESS I2C_BASE_ADDR
 #define    IIC_MDBUF	(I2C_REGISTERS_BASE_ADDRESS+IICMDBUF)
diff --git a/include/440gx_enet.h b/include/440gx_enet.h
index 190b454..45c2f46 100644
--- a/include/440gx_enet.h
+++ b/include/440gx_enet.h
@@ -130,9 +130,9 @@
 } EMAC_440GX_HW_ST, *EMAC_440GX_HW_PST;
 
 
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
 #define EMAC_NUM_DEV	    4
-#elif defined(CONFIG_440) && !defined(CONFIG_440_GX)
+#elif defined(CONFIG_440) && !defined(CONFIG_440GX)
 #define EMAC_NUM_DEV	    2
 #else
 #warning Bad configuration
@@ -140,7 +140,7 @@
 
 
 /*ZMII Bridge Register addresses */
-#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
 #define ZMII_BASE			(CFG_PERIPHERAL_BASE + 0x0D00)
 #else
 #define ZMII_BASE			(CFG_PERIPHERAL_BASE + 0x0780)
@@ -212,7 +212,7 @@
 /*---------------------------------------------------------------------------+
 |  TCP/IP Acceleration Hardware (TAH) 440GX Only
 +---------------------------------------------------------------------------*/
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
 #define TAH_BASE		(CFG_PERIPHERAL_BASE + 0x0B50)
 #define TAH_REVID		(TAH_BASE + 0x0)    /* Revision ID (RO)*/
 #define TAH_MR			(TAH_BASE + 0x10)   /* Mode Register (R/W) */
@@ -272,11 +272,11 @@
 #define TAH_TSR_TFPE		(0x00080000)	    /* Transmit FIFO parity error */
 #define TAH_TSR_SSTS		(0x00040000)	    /* Segment size too small */
 #define TAH_TSR_RSVD		(0x0003FFFF)	    /* Reserved */
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
 
 
 /* Ethernet MAC Regsiter Addresses */
-#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
 #define EMAC_BASE			    (CFG_PERIPHERAL_BASE + 0x0E00)
 #else
 #define EMAC_BASE			    (CFG_PERIPHERAL_BASE + 0x0800)
@@ -319,7 +319,7 @@
 #define EMAC_M0_WKE			    (0x04000000)
 
 /* on 440GX EMAC_MR1 has a different layout! */
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
 /* MODE Reg 1 */
 #define EMAC_M1_FDE		(0x80000000)
 #define EMAC_M1_ILE		(0x40000000)
@@ -349,7 +349,7 @@
 #define EMAC_M1_OBCI_83		(0x00000010)
 #define EMAC_M1_OBCI_66		(0x00000008)
 #define EMAC_M1_RSVD1		(0x00000007)
-#else /* defined(CONFIG_440_GX) */
+#else /* defined(CONFIG_440GX) */
 /* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */
 #define EMAC_M1_FDE			0x80000000
 #define EMAC_M1_ILE			0x40000000
@@ -369,10 +369,10 @@
 #define EMAC_M1_TR0_MULTI		0x00008000
 #define EMAC_M1_TR1_DEPEND		0x00004000
 #define EMAC_M1_TR1_MULTI		0x00002000
-#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
 #define EMAC_M1_JUMBO_ENABLE		0x00001000
-#endif /* defined(CONFIG_440_EP) || defined(CONFIG_440_GR) */
-#endif /* defined(CONFIG_440_GX) */
+#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
+#endif /* defined(CONFIG_440GX) */
 
 /* Transmit Mode Register 0 */
 #define EMAC_TXM0_GNP0			(0x80000000)
diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h
index 5b6cd6f..161a295 100644
--- a/include/asm-ppc/u-boot.h
+++ b/include/asm-ppc/u-boot.h
@@ -101,19 +101,19 @@
 	unsigned char   bi_enet3addr[6];
 #endif
 
-#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined (CONFIG_440_GX) || \
-    defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
+#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined (CONFIG_440GX) || \
+    defined(CONFIG_440EP) || defined(CONFIG_440GR)
 	unsigned int	bi_opbfreq;		/* OPB clock in Hz */
 	int		bi_iic_fast[2];		/* Use fast i2c mode */
 #endif
 #if defined(CONFIG_NX823)
 	unsigned char	bi_sernum[8];
 #endif
-#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
 	int 		bi_phynum[2];           /* Determines phy mapping */
 	int 		bi_phymode[2];          /* Determines phy mode */
 #endif
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
 	int 		bi_phynum[4];           /* Determines phy mapping */
 	int 		bi_phymode[4];          /* Determines phy mode */
 #endif
diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h
index 0235700..347bb50 100644
--- a/include/configs/XPEDITE1K.h
+++ b/include/configs/XPEDITE1K.h
@@ -36,7 +36,7 @@
 #define CONFIG_XPEDITE1K	1		/* Board is XPedite 1000 */
 #define CONFIG_4xx		1		/* ... PPC4xx family	*/
 #define CONFIG_440		1
-#define CONFIG_440_GX		1		/* 440 GX */
+#define CONFIG_440GX		1		/* 440 GX */
 #define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_pre_init	*/
 #undef	CFG_DRAM_TEST				/* Disable-takes long time! */
 #define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll */
diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
index bb5685a..88bbadf 100644
--- a/include/configs/bamboo.h
+++ b/include/configs/bamboo.h
@@ -31,7 +31,7 @@
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
 #define CONFIG_BAMBOO		1	/* Board is BAMBOO              */
-#define CONFIG_440_EP		1	/* Specific PPC440EP support    */
+#define CONFIG_440EP		1	/* Specific PPC440EP support    */
 
 #define CONFIG_4xx		1	/* ... PPC4xx family	        */
 #define CONFIG_BOARD_EARLY_INIT_F 	1   /* Call board_early_init_f	*/
@@ -219,14 +219,14 @@
 #define CONFIG_DOS_PARTITION
 #define CONFIG_ISO_PARTITION
 
-#ifdef CONFIG_440_EP
+#ifdef CONFIG_440EP
 /* USB */
 #define CONFIG_USB_OHCI
 #define CONFIG_USB_STORAGE
 
 /*Comment this out to enable USB 1.1 device*/
 #define USB_2_0_DEVICE
-#endif /*CONFIG_440_EP*/
+#endif /*CONFIG_440EP*/
 
 #define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
 				CFG_CMD_ASKENV	| \
diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h
index 4f90b1b..2b0f687 100644
--- a/include/configs/ocotea.h
+++ b/include/configs/ocotea.h
@@ -40,7 +40,7 @@
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
 #define CONFIG_OCOTEA		1	    /* Board is ebony		*/
-#define CONFIG_440_GX		1	    /* Specifc GX support	*/
+#define CONFIG_440GX		1	    /* Specifc GX support	*/
 #define CONFIG_4xx		1	    /* ... PPC4xx family	*/
 #define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_pre_init	*/
 #undef	CFG_DRAM_TEST			    /* Disable-takes long time! */
diff --git a/include/configs/yellowstone.h b/include/configs/yellowstone.h
index d83d8e7..2b86337 100644
--- a/include/configs/yellowstone.h
+++ b/include/configs/yellowstone.h
@@ -29,7 +29,7 @@
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
 #define CONFIG_YELLOWSTONE			1	/* Board is BAMBOO	     */
-#define CONFIG_440_GR				1	/* Specific PPC440GR support */
+#define CONFIG_440GR				1	/* Specific PPC440GR support */
 
 #define CONFIG_4xx					1	/* ... PPC4xx family	*/
 #define CONFIG_BOARD_EARLY_INIT_F	1   /* Call board_early_init_f	*/
@@ -161,14 +161,14 @@
 #define CONFIG_DOS_PARTITION
 #define CONFIG_ISO_PARTITION
 
-#ifdef CONFIG_440_EP
+#ifdef CONFIG_440EP
 /* USB */
 #define CONFIG_USB_OHCI
 #define CONFIG_USB_STORAGE
 
 /*Comment this out to enable USB 1.1 device*/
 #define USB_2_0_DEVICE
-#endif /*CONFIG_440_EP*/
+#endif /*CONFIG_440EP*/
 
 #ifdef DEBUG
 #define CONFIG_PANIC_HANG
@@ -176,7 +176,7 @@
 #define CONFIG_HW_WATCHDOG			/* watchdog */
 #endif
 
-#ifdef CONFIG_440_EP
+#ifdef CONFIG_440EP
 	/* Need to define POST */
 #define CONFIG_COMMANDS	       ((CONFIG_CMD_DFL | \
 			CFG_CMD_DATE	|   \
diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h
index 18d6623..ddc9169 100644
--- a/include/configs/yosemite.h
+++ b/include/configs/yosemite.h
@@ -29,7 +29,7 @@
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
 #define CONFIG_YOSEMITE				1	/* Board is BAMBOO	     */
-#define CONFIG_440_EP				1	/* Specific PPC440EP support */
+#define CONFIG_440EP				1	/* Specific PPC440EP support */
 
 #define CONFIG_4xx					1	/* ... PPC4xx family	*/
 #define CONFIG_BOARD_EARLY_INIT_F	1   /* Call board_early_init_f	*/
@@ -175,14 +175,14 @@
 #define CONFIG_DOS_PARTITION
 #define CONFIG_ISO_PARTITION
 
-#ifdef CONFIG_440_EP
+#ifdef CONFIG_440EP
 /* USB */
 #define CONFIG_USB_OHCI
 #define CONFIG_USB_STORAGE
 
 /*Comment this out to enable USB 1.1 device*/
 #define USB_2_0_DEVICE
-#endif /*CONFIG_440_EP*/
+#endif /*CONFIG_440EP*/
 
 #ifdef DEBUG
 #define CONFIG_PANIC_HANG
@@ -190,7 +190,7 @@
 #define CONFIG_HW_WATCHDOG			/* watchdog */
 #endif
 
-#ifdef CONFIG_440_EP
+#ifdef CONFIG_440EP
 	/* Need to define POST */
 #define CONFIG_COMMANDS	       ((CONFIG_CMD_DFL | \
 			CFG_CMD_DATE	|   \
diff --git a/include/ppc440.h b/include/ppc440.h
index 874fe343..02f0a2e 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -78,7 +78,7 @@
 #define	 ivor13 0x19d	/* interrupt vector offset register 13 */
 #define	 ivor14 0x19e	/* interrupt vector offset register 14 */
 #define	 ivor15 0x19f	/* interrupt vector offset register 15 */
-#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
 #define	 mcsrr0 0x23a	/* machine check save/restore register 0 */
 #define	 mcsrr1 0x23b	/* mahcine check save/restore register 1 */
 #define	 mcsr	0x23c	/* machine check status register */
@@ -241,7 +241,7 @@
 #define xbcfg		0x23	/* external bus configuration reg	*/
 #define xbcid		0x23	/* external bus core id reg		*/
 
-#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
 
 /* PLB4 to PLB3 Bridge OUT */
 #define P4P3_DCR_BASE           0x020
@@ -504,7 +504,7 @@
 /*-----------------------------------------------------------------------------
  | L2 Cache
  +----------------------------------------------------------------------------*/
-#if defined (CONFIG_440_GX)
+#if defined (CONFIG_440GX)
 #define L2_CACHE_BASE	0x030
 #define l2_cache_cfg	(L2_CACHE_BASE+0x00)	/* L2 Cache Config	*/
 #define l2_cache_cmd	(L2_CACHE_BASE+0x01)	/* L2 Cache Command	*/
@@ -515,8 +515,8 @@
 #define l2_cache_snp0	(L2_CACHE_BASE+0x06)	/* L2 Cache Snoop reg 0 */
 #define l2_cache_snp1	(L2_CACHE_BASE+0x07)	/* L2 Cache Snoop reg 1 */
 
-#endif /* CONFIG_440_GX */
-#endif /* !CONFIG_440_EP !CONFIG_440_GR*/
+#endif /* CONFIG_440GX */
+#endif /* !CONFIG_440EP !CONFIG_440GR*/
 
 /*-----------------------------------------------------------------------------
  | On-Chip Buses
@@ -527,7 +527,7 @@
  | Clocking, Power Management and Chip Control
  +----------------------------------------------------------------------------*/
 #define CNTRL_DCR_BASE 0x0b0
-#if defined (CONFIG_440_GX)
+#if defined (CONFIG_440GX)
 #define cpc0_er		(CNTRL_DCR_BASE+0x00)	/* CPM enable register		*/
 #define cpc0_fr		(CNTRL_DCR_BASE+0x01)	/* CPM force register		*/
 #define cpc0_sr		(CNTRL_DCR_BASE+0x02)	/* CPM status register		*/
@@ -573,7 +573,7 @@
 #define uic1vr	(UIC1_DCR_BASE+0x7)   /* UIC1 vector			   */
 #define uic1vcr (UIC1_DCR_BASE+0x8)   /* UIC1 vector configuration	   */
 
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
 #define UIC2_DCR_BASE 0x210
 #define uic2sr	(UIC2_DCR_BASE+0x0)   /* UIC2 status			   */
 #define uic2er	(UIC2_DCR_BASE+0x2)   /* UIC2 enable			   */
@@ -594,7 +594,7 @@
 #define uicb0msr (UIC_DCR_BASE+0x6)   /* UIC Base masked status		   */
 #define uicb0vr	 (UIC_DCR_BASE+0x7)   /* UIC Base vector		   */
 #define uicb0vcr (UIC_DCR_BASE+0x8)   /* UIC Base vector configuration	   */
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
 
 /* The following is for compatibility with 405 code */
 #define uicsr  uic0sr
@@ -673,16 +673,16 @@
 #define maltxctp3r  (MAL_DCR_BASE+0x23) /* TX 3 Channel table pointer reg   */
 #define malrxctp0r  (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg   */
 #define malrxctp1r  (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg   */
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
 #define malrxctp2r  (MAL_DCR_BASE+0x42) /* RX 0 Channel table pointer reg   */
 #define malrxctp3r  (MAL_DCR_BASE+0x43) /* RX 1 Channel table pointer reg   */
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
 #define malrcbs0    (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg	    */
 #define malrcbs1    (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg	    */
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
 #define malrcbs2    (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg	    */
 #define malrcbs3    (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg	    */
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
 
 
 /*---------------------------------------------------------------------------+
@@ -770,7 +770,7 @@
 /*---------------------------------------------------------------------------+
 |  Universal interrupt controller 2 interrupts (UIC2)
 +---------------------------------------------------------------------------*/
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
 #define UIC_ETH2	0x80000000	/* Ethernet 2			    */
 #define UIC_EWU2	0x40000000	/* Ethernet 2 wakeup		    */
 #define UIC_ETH3	0x20000000	/* Ethernet 3			    */
@@ -803,12 +803,12 @@
 #define UIC_RSVD29	0x00000004	/* Reserved			    */
 #define UIC_RSVD30	0x00000002	/* Reserved			    */
 #define UIC_RSVD31	0x00000001	/* Reserved			    */
-#endif	/* CONFIG_440_GX */
+#endif	/* CONFIG_440GX */
 
 /*---------------------------------------------------------------------------+
 |  Universal interrupt controller Base 0 interrupts (UICB0)
 +---------------------------------------------------------------------------*/
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
 #define UICB0_UIC0CI	0x80000000	/* UIC0 Critical Interrupt	    */
 #define UICB0_UIC0NCI	0x40000000	/* UIC0 Noncritical Interrupt	    */
 #define UICB0_UIC1CI	0x20000000	/* UIC1 Critical Interrupt	    */
@@ -818,7 +818,7 @@
 
 #define UICB0_ALL		(UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \
 						 UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI)
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
 
 /*-----------------------------------------------------------------------------+
 |  External Bus Controller Bit Settings
@@ -1194,7 +1194,7 @@
 /*-----------------------------------------------------------------------------+
 |  Clocking
 +-----------------------------------------------------------------------------*/
-#if !defined (CONFIG_440_GX) && !defined(CONFIG_440_EP) && !defined(CONFIG_440_GR)
+#if !defined (CONFIG_440GX) && !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
 #define PLLSYS0_TUNE_MASK	0xffc00000	/* PLL TUNE bits	    */
 #define PLLSYS0_FB_DIV_MASK	0x003c0000	/* Feedback divisor	    */
 #define PLLSYS0_FWD_DIV_A_MASK	0x00038000	/* Forward divisor A	    */
@@ -1212,7 +1212,7 @@
 #define PLL_VCO_FREQ_MAX	1000		/* Max VCO freq (MHz)	    */
 #define PLL_CPU_FREQ_MAX	400		/* Max CPU freq (MHz)	    */
 #define PLL_PLB_FREQ_MAX	133		/* Max PLB freq (MHz)	    */
-#else /* !CONFIG_440_GX or CONFIG_440_EP or CONFIG_440_GR */
+#else /* !CONFIG_440GX or CONFIG_440EP or CONFIG_440GR */
 #define PLLSYS0_ENG_MASK	0x80000000	/* 0 = SysClk, 1 = PLL VCO */
 #define PLLSYS0_SRC_MASK	0x40000000	/* 0 = PLL A, 1 = PLL B */
 #define PLLSYS0_SEL_MASK	0x38000000	/* 0 = PLL, 1 = CPU, 5 = PerClk */
@@ -1260,7 +1260,7 @@
 #define PLLSYS1_RMII_MASK	0x00000004	/* RMII Mode */
 #define PLLSYS1_TRE_MASK	0x00000002	/* GPIO Trace Enable */
 #define PLLSYS1_NTO1_MASK	0x00000001	/* CPU:PLB N-to-1 ratio */
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
 
 /*-----------------------------------------------------------------------------
 | IIC Register Offsets
@@ -1303,7 +1303,7 @@
 #define PCIX0_CFGBASE		(CFG_PCI_BASE + 0x0ec80000)
 #define PCIX0_IOBASE		(CFG_PCI_BASE + 0x08000000)
 
-#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
 
 /* PCI Local Configuration Registers
    --------------------------------- */
@@ -1387,12 +1387,12 @@
 
 #define PCIX0_STS		(PCIX0_CFGBASE + 0x00e0)
 
-#endif /* !defined(CONFIG_440_EP) !defined(CONFIG_440_GR) */
+#endif /* !defined(CONFIG_440EP) !defined(CONFIG_440GR) */
 
 /******************************************************************************
  * GPIO macro register defines
  ******************************************************************************/
-#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
 #define GPIO_BASE0             (CFG_PERIPHERAL_BASE+0x00000B00)
 #define GPIO_BASE1             (CFG_PERIPHERAL_BASE+0x00000C00)