[Blackfin][PATCH] code cleanup
diff --git a/board/bf533-ezkit/flash.c b/board/bf533-ezkit/flash.c
index 1b56d5b..067a260 100644
--- a/board/bf533-ezkit/flash.c
+++ b/board/bf533-ezkit/flash.c
@@ -26,6 +26,7 @@
* MA 02111-1307 USA
*/
+#include <asm/io.h>
#include "flash-defines.h"
void flash_reset(void)
@@ -282,9 +283,9 @@
long addr;
addr = (CFG_FLASH_BASE + nOffset);
- __builtin_bfin_ssync();
+ sync();
*(unsigned volatile short *)addr = nValue;
- __builtin_bfin_ssync();
+ sync();
if (poll_toggle_bit(nOffset) < 0)
return FLASH_FAIL;
return FLASH_SUCCESS;
@@ -297,9 +298,9 @@
if (nOffset != 0x2)
reset_flash();
- __builtin_bfin_ssync();
+ sync();
nValue = *(volatile unsigned short *)addr;
- __builtin_bfin_ssync();
+ sync();
*pnValue = nValue;
return TRUE;
}
diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c
index 3e074e3..2f6e751 100644
--- a/board/bf533-stamp/bf533-stamp.c
+++ b/board/bf533-stamp/bf533-stamp.c
@@ -27,6 +27,7 @@
#include <common.h>
#include <asm/mem_init.h>
+#include <asm/io.h>
#include "bf533-stamp.h"
#define STATUS_LED_OFF 0
@@ -74,9 +75,9 @@
if (device_id == ETHERNET) {
*pFIO_DIR = PF0;
- __builtin_bfin_ssync();
+ sync();
*pFIO_FLAG_S = PF0;
- __builtin_bfin_ssync();
+ sync();
} else if (device_id == FLASH) {
*pFIO_DIR = (PF4 | PF3 | PF2 | PF1 | PF0);
*pFIO_FLAG_S = (PF4 | PF3 | PF2);
@@ -86,7 +87,7 @@
*pFIO_EDGE = (PF8 | PF7 | PF6 | PF5);
*pFIO_INEN = (PF8 | PF7 | PF6 | PF5);
*pFIO_FLAG_D = (PF4 | PF3 | PF2);
- __builtin_bfin_ssync();
+ sync();
} else {
printf("Unknown bank to switch\n");
}
@@ -153,15 +154,15 @@
*/
*pFIO_FLAG_S = CF_PF0;
*pFIO_FLAG_C = CF_PF1;
- __builtin_bfin_ssync();
+ sync();
*(addr) = val;
- __builtin_bfin_ssync();
+ sync();
/* Setback PF1 PF0 to 0 0 to address external
* memory banks */
*(volatile unsigned short *)pFIO_FLAG_C = CF_PF1_PF0;
- __builtin_bfin_ssync();
+ sync();
}
unsigned char cf_inb(volatile unsigned char *addr)
@@ -170,13 +171,13 @@
*pFIO_FLAG_S = CF_PF0;
*pFIO_FLAG_C = CF_PF1;
- __builtin_bfin_ssync();
+ sync();
c = *(addr);
- __builtin_bfin_ssync();
+ sync();
*pFIO_FLAG_C = CF_PF1_PF0;
- __builtin_bfin_ssync();
+ sync();
return c;
}
@@ -187,15 +188,15 @@
*pFIO_FLAG_S = CF_PF0;
*pFIO_FLAG_C = CF_PF1;
- __builtin_bfin_ssync();
+ sync();
for (i = 0; i < words; i++) {
*(sect_buf + i) = *(addr);
- __builtin_bfin_ssync();
+ sync();
}
*pFIO_FLAG_C = CF_PF1_PF0;
- __builtin_bfin_ssync();
+ sync();
}
void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
@@ -204,15 +205,15 @@
*pFIO_FLAG_S = CF_PF0;
*pFIO_FLAG_C = CF_PF1;
- __builtin_bfin_ssync();
+ sync();
for (i = 0; i < words; i++) {
*(addr) = *(sect_buf + i);
- __builtin_bfin_ssync();
+ sync();
}
*pFIO_FLAG_C = CF_PF1_PF0;
- __builtin_bfin_ssync();
+ sync();
}
#endif
@@ -233,7 +234,7 @@
*pFIO_FLAG_S = PF4;
else
*pFIO_FLAG_C = PF4;
- __builtin_bfin_ssync();
+ sync();
}
void show_boot_progress(int status)
diff --git a/board/bf533-stamp/spi.c b/board/bf533-stamp/spi.c
index 1b585aa..d30750f 100644
--- a/board/bf533-stamp/spi.c
+++ b/board/bf533-stamp/spi.c
@@ -3,6 +3,7 @@
****************************************************************************/
#include <common.h>
#include <linux/ctype.h>
+#include <asm/io.h>
#if defined(CONFIG_SPI)
@@ -152,7 +153,7 @@
/*sends the actual command to the SPI TX register */
*pSPI_TDBR = iCommand;
- __builtin_bfin_ssync();
+ sync();
/*The SPI status register will be polled to check the SPIF bit */
Wait_For_SPIF();
@@ -173,7 +174,7 @@
*pSPI_FLG = 0xFB04;
*pSPI_BAUD = CONFIG_SPI_BAUD;
*pSPI_CTL = spi_setting;
- __builtin_bfin_ssync();
+ sync();
}
void SPI_OFF(void)
@@ -182,7 +183,7 @@
*pSPI_CTL = 0x0400; /* disable SPI */
*pSPI_FLG = 0;
*pSPI_BAUD = 0;
- __builtin_bfin_ssync();
+ sync();
udelay(CONFIG_CCLK_HZ / 50000000);
}
@@ -240,10 +241,10 @@
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01)); /* Turn on the SPI */
*pSPI_TDBR = SPI_RDSR; /* send instruction to read status register */
- __builtin_bfin_ssync();
+ sync();
Wait_For_SPIF(); /*wait until the instruction has been sent */
*pSPI_TDBR = 0; /*send dummy to receive the status register */
- __builtin_bfin_ssync();
+ sync();
Wait_For_SPIF(); /*wait until the data has been sent */
status_register = *pSPI_RDBR; /*read the status register */
@@ -304,18 +305,18 @@
/* Send the erase block command to the flash followed by the 24 address */
/* to point to the start of a sector. */
*pSPI_TDBR = SPI_SE;
- __builtin_bfin_ssync();
+ sync();
Wait_For_SPIF();
ShiftValue = (ulSectorOff >> 16); /* Send the highest byte of the 24 bit address at first */
*pSPI_TDBR = ShiftValue;
- __builtin_bfin_ssync();
+ sync();
Wait_For_SPIF(); /* Wait until the instruction has been sent */
ShiftValue = (ulSectorOff >> 8); /* Send the middle byte of the 24 bit address at second */
*pSPI_TDBR = ShiftValue;
- __builtin_bfin_ssync();
+ sync();
Wait_For_SPIF(); /* Wait until the instruction has been sent */
*pSPI_TDBR = ulSectorOff; /* Send the lowest byte of the 24 bit address finally */
- __builtin_bfin_ssync();
+ sync();
Wait_For_SPIF(); /* Wait until the instruction has been sent */
/*Turns off the SPI */
@@ -350,25 +351,25 @@
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
*pSPI_TDBR = SPI_READ; /* Send the read command to SPI device */
- __builtin_bfin_ssync();
+ sync();
Wait_For_SPIF(); /* Wait until the instruction has been sent */
ShiftValue = (ulStart >> 16); /* Send the highest byte of the 24 bit address at first */
*pSPI_TDBR = ShiftValue; /* Send the byte to the SPI device */
- __builtin_bfin_ssync();
+ sync();
Wait_For_SPIF(); /* Wait until the instruction has been sent */
ShiftValue = (ulStart >> 8); /* Send the middle byte of the 24 bit address at second */
*pSPI_TDBR = ShiftValue; /* Send the byte to the SPI device */
- __builtin_bfin_ssync();
+ sync();
Wait_For_SPIF(); /* Wait until the instruction has been sent */
*pSPI_TDBR = ulStart; /* Send the lowest byte of the 24 bit address finally */
- __builtin_bfin_ssync();
+ sync();
Wait_For_SPIF(); /* Wait until the instruction has been sent */
/* After the SPI device address has been placed on the MOSI pin the data can be */
/* received on the MISO pin. */
for (i = 0; i < lCount; i++) {
*pSPI_TDBR = 0; /*send dummy */
- __builtin_bfin_ssync();
+ sync();
while (!(*pSPI_STAT & RXS)) ;
*cnData++ = *pSPI_RDBR; /*read */
@@ -405,26 +406,26 @@
/* Third, the 24 bit address will be shifted out the SPI MOSI bytewise. */
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01)); /* Turns the SPI on */
*pSPI_TDBR = SPI_PP;
- __builtin_bfin_ssync();
+ sync();
Wait_For_SPIF(); /*wait until the instruction has been sent */
ulWAddr = (ulStartAddr >> 16);
*pSPI_TDBR = ulWAddr;
- __builtin_bfin_ssync();
+ sync();
Wait_For_SPIF(); /*wait until the instruction has been sent */
ulWAddr = (ulStartAddr >> 8);
*pSPI_TDBR = ulWAddr;
- __builtin_bfin_ssync();
+ sync();
Wait_For_SPIF(); /*wait until the instruction has been sent */
ulWAddr = ulStartAddr;
*pSPI_TDBR = ulWAddr;
- __builtin_bfin_ssync();
+ sync();
Wait_For_SPIF(); /*wait until the instruction has been sent */
/* Fourth, maximum number of 256 bytes will be taken from the Buffer */
/* and sent to the SPI device. */
for (i = 0; (i < lTransferCount) && (i < 256); i++, lWTransferCount++) {
iData = *temp;
*pSPI_TDBR = iData;
- __builtin_bfin_ssync();
+ sync();
Wait_For_SPIF(); /*wait until the instruction has been sent */
temp++;
}