* Patch by Markus Pietrek, 24 Feb 2004:
NS9750 DevBoard added
* Patch by Pierre AUBERT, 24 Feb 2004
add USB support for MPC5200
* Patch by Steven Scholz, 24 Feb 2004:
- fix MII commands to use values from last command
* Patch by Torsten Demke, 24 Feb 2004:
Add support for the eXalion platform (SPSW-8240, F-30, F-300)
diff --git a/board/eXalion/Makefile b/board/eXalion/Makefile
new file mode 100644
index 0000000..110d09d
--- /dev/null
+++ b/board/eXalion/Makefile
@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o
+SOBJS =
+
+$(LIB): .depend $(OBJS) $(SOBJS)
+ $(AR) crv $@ $^
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/eXalion/config.mk b/board/eXalion/config.mk
new file mode 100644
index 0000000..b3f65eb
--- /dev/null
+++ b/board/eXalion/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2000, 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Sandpoint boards
+#
+
+#TEXT_BASE = 0x00090000
+TEXT_BASE = 0xFFF00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
diff --git a/board/eXalion/eXalion.c b/board/eXalion/eXalion.c
new file mode 100644
index 0000000..2e3f519
--- /dev/null
+++ b/board/eXalion/eXalion.c
@@ -0,0 +1,292 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * Torsten Demke, FORCE Computers GmbH. torsten.demke@fci.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <pci.h>
+#include <ide.h>
+#include "piix_pci.h"
+#include "eXalion.h"
+
+int checkboard (void)
+{
+ ulong busfreq = get_bus_freq (0);
+ char buf[32];
+
+ printf ("Board: eXalion MPC824x - CHRP (MAP B)\n");
+ printf ("Built: %s at %s\n", __DATE__, __TIME__);
+ printf ("Local Bus: %s MHz\n", strmhz (buf, busfreq));
+
+ return 0;
+}
+
+int checkflash (void)
+{
+ printf ("checkflash\n");
+ flash_init ();
+ return (0);
+}
+
+long int initdram (int board_type)
+{
+ int i, cnt;
+ volatile uchar *base = CFG_SDRAM_BASE;
+ volatile ulong *addr;
+ ulong save[32];
+ ulong val, ret = 0;
+
+ for (i = 0, cnt = (CFG_MAX_RAM_SIZE / sizeof (long)) >> 1; cnt > 0;
+ cnt >>= 1) {
+ addr = (volatile ulong *) base + cnt;
+ save[i++] = *addr;
+ *addr = ~cnt;
+ }
+
+ addr = (volatile ulong *) base;
+ save[i] = *addr;
+ *addr = 0;
+
+ if (*addr != 0) {
+ *addr = save[i];
+ goto Done;
+ }
+
+ for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof (long); cnt <<= 1) {
+ addr = (volatile ulong *) base + cnt;
+ val = *addr;
+ *addr = save[--i];
+ if (val != ~cnt) {
+ ulong new_bank0_end = cnt * sizeof (long) - 1;
+ ulong mear1 = mpc824x_mpc107_getreg (MEAR1);
+ ulong emear1 = mpc824x_mpc107_getreg (EMEAR1);
+
+ mear1 = (mear1 & 0xFFFFFF00) |
+ ((new_bank0_end & MICR_ADDR_MASK) >>
+ MICR_ADDR_SHIFT);
+ emear1 = (emear1 & 0xFFFFFF00) |
+ ((new_bank0_end & MICR_ADDR_MASK) >>
+ MICR_EADDR_SHIFT);
+ mpc824x_mpc107_setreg (MEAR1, mear1);
+ mpc824x_mpc107_setreg (EMEAR1, emear1);
+
+ ret = cnt * sizeof (long);
+ goto Done;
+ }
+ }
+
+ ret = CFG_MAX_RAM_SIZE;
+ Done:
+ return ret;
+}
+
+int misc_init_r (void)
+{
+ pci_dev_t bdf;
+ u32 val32;
+ u8 val8;
+
+ puts ("ISA: ");
+ bdf = pci_find_device (PIIX4_VENDOR_ID, PIIX4_ISA_DEV_ID, 0);
+ if (bdf == -1) {
+ puts ("Unable to find PIIX4 ISA bridge !\n");
+ hang ();
+ }
+
+ /* set device for normal ISA instead EIO */
+ pci_read_config_dword (bdf, PCI_CFG_PIIX4_GENCFG, &val32);
+ val32 |= 0x00000001;
+ pci_write_config_dword (bdf, PCI_CFG_PIIX4_GENCFG, val32);
+ printf ("PIIX4 ISA bridge (%d,%d,%d)\n", PCI_BUS (bdf),
+ PCI_DEV (bdf), PCI_FUNC (bdf));
+
+ puts ("ISA: ");
+ bdf = pci_find_device (PIIX4_VENDOR_ID, PIIX4_IDE_DEV_ID, 0);
+ if (bdf == -1) {
+ puts ("Unable to find PIIX4 IDE controller !\n");
+ hang ();
+ }
+
+ /* Init BMIBA register */
+ /* pci_read_config_dword(bdf, PCI_CFG_PIIX4_BMIBA, &val32); */
+ /* val32 |= 0x1000; */
+ /* pci_write_config_dword(bdf, PCI_CFG_PIIX4_BMIBA, val32); */
+
+ /* Enable BUS master and IO access */
+ val32 = PCI_COMMAND_MASTER | PCI_COMMAND_IO;
+ pci_write_config_dword (bdf, PCI_COMMAND, val32);
+
+ /* Set latency */
+ pci_read_config_byte (bdf, PCI_LATENCY_TIMER, &val8);
+ val8 = 0x40;
+ pci_write_config_byte (bdf, PCI_LATENCY_TIMER, val8);
+
+ /* Enable Primary ATA/IDE */
+ pci_read_config_dword (bdf, PCI_CFG_PIIX4_IDETIM, &val32);
+ /* val32 = 0xa307a307; */
+ val32 = 0x00008000;
+ pci_write_config_dword (bdf, PCI_CFG_PIIX4_IDETIM, val32);
+
+
+ printf ("PIIX4 IDE controller (%d,%d,%d)\n", PCI_BUS (bdf),
+ PCI_DEV (bdf), PCI_FUNC (bdf));
+
+ /* Try to get FAT working... */
+ /* fat_register_read(ide_read); */
+
+
+ return (0);
+}
+
+/*
+ * Show/Init PCI devices on the specified bus number.
+ */
+
+void pci_eXalion_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
+{
+ unsigned char line;
+
+ switch (PCI_DEV (dev)) {
+ case 16:
+ line = PCI_INT_A;
+ break;
+ case 17:
+ line = PCI_INT_B;
+ break;
+ case 18:
+ line = PCI_INT_C;
+ break;
+ case 19:
+ line = PCI_INT_D;
+ break;
+#if defined (CONFIG_MPC8245)
+ case 20:
+ line = PCI_INT_A;
+ break;
+ case 21:
+ line = PCI_INT_B;
+ break;
+ case 22:
+ line = PCI_INT_NA;
+ break;
+#endif
+ default:
+ line = PCI_INT_A;
+ break;
+ }
+ pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, line);
+}
+
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+#ifndef CONFIG_PCI_PNP
+#if defined (CONFIG_MPC8240)
+static struct pci_config_table pci_eXalion_config_table[] = {
+ {
+ /* Intel 82559ER ethernet controller */
+ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 18, 0x00,
+ pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+ PCI_ENET0_MEMADDR,
+ PCI_COMMAND_MEMORY |
+ PCI_COMMAND_MASTER}},
+ {
+ /* Intel 82371AB PIIX4 PCI to ISA bridge */
+ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x00,
+ pci_cfgfunc_config_device, {0,
+ 0,
+ PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
+ {
+ /* Intel 82371AB PIIX4 IDE controller */
+ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x01,
+ pci_cfgfunc_config_device, {0,
+ 0,
+ PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
+ {}
+};
+#elif defined (CONFIG_MPC8245)
+static struct pci_config_table pci_eXalion_config_table[] = {
+ {
+ /* Intel 82559ER ethernet controller */
+ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 17, 0x00,
+ pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+ PCI_ENET0_MEMADDR,
+ PCI_COMMAND_MEMORY |
+ PCI_COMMAND_MASTER}},
+ {
+ /* Intel 82559ER ethernet controller */
+ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 18, 0x00,
+ pci_cfgfunc_config_device, {PCI_ENET1_IOADDR,
+ PCI_ENET1_MEMADDR,
+ PCI_COMMAND_MEMORY |
+ PCI_COMMAND_MASTER}},
+ {
+ /* Broadcom BCM5690 Gigabit switch */
+ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x00,
+ pci_cfgfunc_config_device, {PCI_ENET2_IOADDR,
+ PCI_ENET2_MEMADDR,
+ PCI_COMMAND_MEMORY |
+ PCI_COMMAND_MASTER}},
+ {
+ /* Broadcom BCM5690 Gigabit switch */
+ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 21, 0x00,
+ pci_cfgfunc_config_device, {PCI_ENET3_IOADDR,
+ PCI_ENET3_MEMADDR,
+ PCI_COMMAND_MEMORY |
+ PCI_COMMAND_MASTER}},
+ {
+ /* Intel 82371AB PIIX4 PCI to ISA bridge */
+ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 22, 0x00,
+ pci_cfgfunc_config_device, {0,
+ 0,
+ PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
+ {
+ /* Intel 82371AB PIIX4 IDE controller */
+ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 22, 0x01,
+ pci_cfgfunc_config_device, {0,
+ 0,
+ PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
+ {}
+};
+#else
+#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
+#endif
+
+#endif /* #ifndef CONFIG_PCI_PNP */
+
+struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+ config_table:pci_eXalion_config_table,
+ fixup_irq:pci_eXalion_fixup_irq,
+#endif
+};
+
+void pci_init_board (void)
+{
+ pci_mpc824x_init (&hose);
+}
diff --git a/board/eXalion/eXalion.h b/board/eXalion/eXalion.h
new file mode 100644
index 0000000..8dccabb
--- /dev/null
+++ b/board/eXalion/eXalion.h
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2002
+ * Torsten Demke, FORCE Computers GmbH. torsten.demke@fci.com
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * James Dougherty (jfd@broadcom.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __EXALION_H
+#define __EXALION_H
+
+/* IRQ settings */
+#define PCI_INT_NA (0xff) /* PCI Intr. not used */
+#define PCI_INT_A (0x09) /* PCI Intr. A Interrupt Request Line Nr. */
+#define PCI_INT_B (0x0a) /* PCI Intr. B Interrupt Request Line Nr. */
+#define PCI_INT_C (0x0b) /* PCI Intr. C Interrupt Request Line Nr. */
+#define PCI_INT_D (0x0c) /* PCI Intr. D Interrupt Request Line Nr. */
+#if defined (CPU_MPC8245)
+#define LN_1_INT PCI_INT_B /* ethernet interrupt level */
+#define LN_2_INT PCI_INT_C /* ethernet interrupt level */
+#define BCM_1_INT PCI_INT_A /* BCM5690 interrupt level */
+#define BCM_2_INT PCI_INT_B /* BCM5690 interrupt level */
+#elif defined (CPU_MPC8240)
+#define BCM_INT PCI_INT_B /* BCM5600 interrupt level */
+#define LN_INT PCI_INT_C /* ethernet interrupt level */
+#endif
+
+#ifndef __ASSEMBLY__
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __EXALION_H */
diff --git a/board/eXalion/piix_pci.h b/board/eXalion/piix_pci.h
new file mode 100644
index 0000000..b3c9c16
--- /dev/null
+++ b/board/eXalion/piix_pci.h
@@ -0,0 +1,172 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * Torsten Demke, FORCE Computers GmbH. torsten.demke@fci.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _PIIX4_PCI_H
+#define _PIIX4_PCI_H
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <pci.h>
+
+#define PIIX4_VENDOR_ID 0x8086
+#define PIIX4_ISA_DEV_ID 0x7110
+#define PIIX4_IDE_DEV_ID 0x7111
+
+/* Function 0 ISA Bridge */
+#define PCI_CFG_PIIX4_IORT 0x4C /* 8 bit ISA Recovery Timer Reg (default 0x4D) */
+#define PCI_CFG_PIIX4_XBCS 0x4E /* 16 bit XBus Chip select reg (default 0x0003) */
+#define PCI_CFG_PIIX4_PIRQC 0x60 /* PCI IRQ Route Register 4 x 8bit (default )*/
+#define PCI_CFG_PIIX4_SERIRQ 0x64
+#define PCI_CFG_PIIX4_TOM 0x69
+#define PCI_CFG_PIIX4_MSTAT 0x6A
+#define PCI_CFG_PIIX4_MBDMA 0x76
+#define PCI_CFG_PIIX4_APICBS 0x80
+#define PCI_CFG_PIIX4_DLC 0x82
+#define PCI_CFG_PIIX4_PDMACFG 0x90
+#define PCI_CFG_PIIX4_DDMABS 0x92
+#define PCI_CFG_PIIX4_GENCFG 0xB0
+#define PCI_CFG_PIIX4_RTCCFG 0xCB
+
+/* IO Addresses */
+#define PIIX4_ISA_DMA1_CH0BA 0x00
+#define PIIX4_ISA_DMA1_CH0CA 0x01
+#define PIIX4_ISA_DMA1_CH1BA 0x02
+#define PIIX4_ISA_DMA1_CH1CA 0x03
+#define PIIX4_ISA_DMA1_CH2BA 0x04
+#define PIIX4_ISA_DMA1_CH2CA 0x05
+#define PIIX4_ISA_DMA1_CH3BA 0x06
+#define PIIX4_ISA_DMA1_CH3CA 0x07
+#define PIIX4_ISA_DMA1_CMDST 0x08
+#define PIIX4_ISA_DMA1_REQ 0x09
+#define PIIX4_ISA_DMA1_WSBM 0x0A
+#define PIIX4_ISA_DMA1_CH_MOD 0x0B
+#define PIIX4_ISA_DMA1_CLR_PT 0x0C
+#define PIIX4_ISA_DMA1_M_CLR 0x0D
+#define PIIX4_ISA_DMA1_CLR_M 0x0E
+#define PIIX4_ISA_DMA1_RWAMB 0x0F
+
+#define PIIX4_ISA_DMA2_CH0BA 0xC0
+#define PIIX4_ISA_DMA2_CH0CA 0xC1
+#define PIIX4_ISA_DMA2_CH1BA 0xC2
+#define PIIX4_ISA_DMA2_CH1CA 0xC3
+#define PIIX4_ISA_DMA2_CH2BA 0xC4
+#define PIIX4_ISA_DMA2_CH2CA 0xC5
+#define PIIX4_ISA_DMA2_CH3BA 0xC6
+#define PIIX4_ISA_DMA2_CH3CA 0xC7
+#define PIIX4_ISA_DMA2_CMDST 0xD0
+#define PIIX4_ISA_DMA2_REQ 0xD2
+#define PIIX4_ISA_DMA2_WSBM 0xD4
+#define PIIX4_ISA_DMA2_CH_MOD 0xD6
+#define PIIX4_ISA_DMA2_CLR_PT 0xD8
+#define PIIX4_ISA_DMA2_M_CLR 0xDA
+#define PIIX4_ISA_DMA2_CLR_M 0xDC
+#define PIIX4_ISA_DMA2_RWAMB 0xDE
+
+#define PIIX4_ISA_INT1_ICW1 0x20
+#define PIIX4_ISA_INT1_OCW2 0x20
+#define PIIX4_ISA_INT1_OCW3 0x20
+#define PIIX4_ISA_INT1_ICW2 0x21
+#define PIIX4_ISA_INT1_ICW3 0x21
+#define PIIX4_ISA_INT1_ICW4 0x21
+#define PIIX4_ISA_INT1_OCW1 0x21
+
+#define PIIX4_ISA_INT1_ELCR 0x4D0
+
+#define PIIX4_ISA_INT2_ICW1 0xA0
+#define PIIX4_ISA_INT2_OCW2 0xA0
+#define PIIX4_ISA_INT2_OCW3 0xA0
+#define PIIX4_ISA_INT2_ICW2 0xA1
+#define PIIX4_ISA_INT2_ICW3 0xA1
+#define PIIX4_ISA_INT2_ICW4 0xA1
+#define PIIX4_ISA_INT2_OCW1 0xA1
+#define PIIX4_ISA_INT2_IMR 0xA1 /* read only */
+
+#define PIIX4_ISA_INT2_ELCR 0x4D1
+
+#define PIIX4_ISA_TMR0_CNT_ST 0x40
+#define PIIX4_ISA_TMR1_CNT_ST 0x41
+#define PIIX4_ISA_TMR2_CNT_ST 0x42
+#define PIIX4_ISA_TMR_TCW 0x43
+
+#define PIIX4_ISA_RST_XBUS 0x60
+
+#define PIIX4_ISA_NMI_CNT_ST 0x61
+#define PIIX4_ISA_NMI_ENABLE 0x70
+
+#define PIIX4_ISA_RTC_INDEX 0x70
+#define PIIX4_ISA_RTC_DATA 0x71
+#define PIIX4_ISA_RTCEXT_IND 0x70
+#define PIIX4_ISA_RTCEXT_DATA 0x71
+
+#define PIIX4_ISA_DMA1_CH2LPG 0x81
+#define PIIX4_ISA_DMA1_CH3LPG 0x82
+#define PIIX4_ISA_DMA1_CH1LPG 0x83
+#define PIIX4_ISA_DMA1_CH0LPG 0x87
+#define PIIX4_ISA_DMA2_CH2LPG 0x89
+#define PIIX4_ISA_DMA2_CH3LPG 0x8A
+#define PIIX4_ISA_DMA2_CH1LPG 0x8B
+#define PIIX4_ISA_DMA2_LPGRFR 0x8F
+
+#define PIIX4_ISA_PORT_92 0x92
+
+#define PIIX4_ISA_APM_CONTRL 0xB2
+#define PIIX4_ISA_APM_STATUS 0xB3
+
+#define PIIX4_ISA_COCPU_ERROR 0xF0
+
+/* Function 1 IDE Controller */
+#define PCI_CFG_PIIX4_BMIBA 0x20
+#define PCI_CFG_PIIX4_IDETIM 0x40
+#define PCI_CFG_PIIX4_SIDETIM 0x44
+#define PCI_CFG_PIIX4_UDMACTL 0x48
+#define PCI_CFG_PIIX4_UDMATIM 0x4A
+
+/* Function 2 USB Controller */
+#define PCI_CFG_PIIX4_SBRNUM 0x60
+#define PCI_CFG_PIIX4_LEGSUP 0xC0
+
+/* Function 3 Power Management */
+#define PCI_CFG_PIIX4_PMAB 0x40
+#define PCI_CFG_PIIX4_CNTA 0x44
+#define PCI_CFG_PIIX4_CNTB 0x48
+#define PCI_CFG_PIIX4_GPICTL 0x4C
+#define PCI_CFG_PIIX4_DEVRESD 0x50
+#define PCI_CFG_PIIX4_DEVACTA 0x54
+#define PCI_CFG_PIIX4_DEVACTB 0x58
+#define PCI_CFG_PIIX4_DEVRESA 0x5C
+#define PCI_CFG_PIIX4_DEVRESB 0x60
+#define PCI_CFG_PIIX4_DEVRESC 0x64
+#define PCI_CFG_PIIX4_DEVRESE 0x68
+#define PCI_CFG_PIIX4_DEVRESF 0x6C
+#define PCI_CFG_PIIX4_DEVRESG 0x70
+#define PCI_CFG_PIIX4_DEVRESH 0x74
+#define PCI_CFG_PIIX4_DEVRESI 0x78
+#define PCI_CFG_PIIX4_PMMISC 0x80
+#define PCI_CFG_PIIX4_SMBBA 0x90
+
+
+#endif /* _PIIX4_PCI_H */
diff --git a/board/eXalion/u-boot.lds b/board/eXalion/u-boot.lds
new file mode 100644
index 0000000..98584dc
--- /dev/null
+++ b/board/eXalion/u-boot.lds
@@ -0,0 +1,133 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc824x/start.o (.text)
+ lib_ppc/board.o (.text)
+ lib_ppc/ppcstring.o (.text)
+ lib_generic/vsprintf.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_generic/zlib.o (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/environment.o (.text)
+
+ *(.text)
+
+ *(.fixup)
+ *(.got1)
+ . = ALIGN(16);
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+
+ _end = . ;
+ PROVIDE (end = .);
+}