Merge branch 'master-spi-fixes' of https://source.denx.de/u-boot/custodians/u-boot-sh
Last minute SPI fixes for R-Car to make the SPI NOR work on Gen4.
Also one RPC HF fix for Gen4.
diff --git a/arch/arm/dts/r8a779g0-u-boot.dtsi b/arch/arm/dts/r8a779g0-u-boot.dtsi
index cc8beca..f60eba5 100644
--- a/arch/arm/dts/r8a779g0-u-boot.dtsi
+++ b/arch/arm/dts/r8a779g0-u-boot.dtsi
@@ -8,7 +8,6 @@
#include "r8a779x-u-boot.dtsi"
&rpc {
- reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>;
bank-width = <2>;
num-cs = <1>;
};
diff --git a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi
index a102639..c3704d7 100644
--- a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi
+++ b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi
@@ -13,29 +13,9 @@
};
};
-&pfc {
- qspi0_pins: qspi0 {
- groups = "qspi0_ctrl", "qspi0_data4";
- function = "qspi0";
- };
-};
-
&rpc {
- pinctrl-0 = <&qspi0_pins>;
- pinctrl-names = "default";
-
- #address-cells = <1>;
- #size-cells = <0>;
- spi-max-frequency = <40000000>;
- status = "disabled";
-
- spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "s25fs512s", "jedec,spi-nor";
- reg = <0>;
+ flash@0 {
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
- spi-max-frequency = <40000000>;
};
};
diff --git a/drivers/mtd/renesas_rpc_hf.c b/drivers/mtd/renesas_rpc_hf.c
index 941f204..0354582 100644
--- a/drivers/mtd/renesas_rpc_hf.c
+++ b/drivers/mtd/renesas_rpc_hf.c
@@ -387,6 +387,7 @@
static const struct udevice_id rpc_hf_ids[] = {
{ .compatible = "renesas,r7s72100-rpc-if" },
{ .compatible = "renesas,rcar-gen3-rpc-if" },
+ { .compatible = "renesas,rcar-gen4-rpc-if" },
{}
};
diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c
index e6b602c..f1e6f9f 100644
--- a/drivers/spi/renesas_rpc_spi.c
+++ b/drivers/spi/renesas_rpc_spi.c
@@ -145,6 +145,12 @@
#define RPC_PHYCNT_WBUF BIT(2)
#define RPC_PHYCNT_MEM(v) (((v) & 0x3) << 0)
+#define RPCIF_PHYOFFSET1 0x0080 /* R/W */
+#define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28)
+
+#define RPCIF_PHYOFFSET2 0x0084 /* R/W */
+#define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8)
+
#define RPC_PHYINT 0x0088 /* R/W */
#define RPC_PHYINT_RSTEN BIT(18)
#define RPC_PHYINT_WPEN BIT(17)
@@ -227,6 +233,12 @@
struct udevice *bus = dev->parent;
struct rpc_spi_priv *priv = dev_get_priv(bus);
+ setbits_le32(priv->regs + RPCIF_PHYOFFSET1,
+ RPCIF_PHYOFFSET1_DDRTMG(3));
+ clrsetbits_le32(priv->regs + RPCIF_PHYOFFSET2,
+ RPCIF_PHYOFFSET2_OCTTMG(7),
+ RPCIF_PHYOFFSET2_OCTTMG(4));
+
/* NOTE: The 0x260 are undocumented bits, but they must be set. */
writel(RPC_PHYCNT_CAL | rpc_spi_get_strobe_delay() | 0x260,
priv->regs + RPC_PHYCNT);
@@ -277,24 +289,24 @@
writel(RPC_DRCMR_CMD(op->cmd.opcode), priv->regs + RPC_DRCMR);
smenr |= RPC_DRENR_CDE;
- writel(0, priv->regs + RPC_DREAR);
if (op->addr.nbytes == 4) {
writel(RPC_DREAR_EAV(offset >> 25) | RPC_DREAR_EAC(1),
priv->regs + RPC_DREAR);
smenr |= RPC_DRENR_ADE(0xF);
} else if (op->addr.nbytes == 3) {
+ writel(0, priv->regs + RPC_DREAR);
smenr |= RPC_DRENR_ADE(0x7);
} else {
+ writel(0, priv->regs + RPC_DREAR);
smenr |= RPC_DRENR_ADE(0);
}
- writel(0, priv->regs + RPC_DRDMCR);
- if (op->dummy.nbytes) {
- writel(8 * op->dummy.nbytes - 1, priv->regs + RPC_DRDMCR);
+ if (op->dummy.nbytes)
smenr |= RPC_DRENR_DME;
- }
+ writel(8 * op->dummy.nbytes - 1, priv->regs + RPC_DRDMCR);
writel(0, priv->regs + RPC_DROPR);
+ writel(0, priv->regs + RPC_DRDRENR);
writel(smenr, priv->regs + RPC_DRENR);
memcpy_fromio(din, (void *)(priv->extr + offset), op->data.nbytes);
@@ -453,6 +465,7 @@
static const struct udevice_id rpc_spi_ids[] = {
{ .compatible = "renesas,r7s72100-rpc-if" },
{ .compatible = "renesas,rcar-gen3-rpc-if" },
+ { .compatible = "renesas,rcar-gen4-rpc-if" },
{ }
};