MIPS: Join the coherent domain when a CM is present
MIPS Linux expects the bootloader to leave the boot CPU a member of the
coherent domain when running on a system with a CM, and we will need to
do so if we wish to make use of IOCUs to have cache-coherent DMA in
U-Boot (and on some systems there is no choice in that matter). When a
CM is present, join the coherent domain after completing cache
initialisation.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
diff --git a/arch/mips/include/asm/cm.h b/arch/mips/include/asm/cm.h
index 62ecef2..b9ab0c6 100644
--- a/arch/mips/include/asm/cm.h
+++ b/arch/mips/include/asm/cm.h
@@ -19,6 +19,7 @@
#define GCR_L2_TAG_STATE_UPPER 0x060c
#define GCR_L2_DATA 0x0610
#define GCR_L2_DATA_UPPER 0x0614
+#define GCR_Cx_COHERENCE 0x2008
/* GCR_REV CM versions */
#define GCR_REV_CM3 0x0800
@@ -32,6 +33,10 @@
#define GCR_L2_CONFIG_SETSZ_BITS 4
#define GCR_L2_CONFIG_BYPASS (1 << 20)
+/* GCR_Cx_COHERENCE */
+#define GCR_Cx_COHERENCE_DOM_EN (0xff << 0)
+#define GCR_Cx_COHERENCE_EN (0x1 << 0)
+
#ifndef __ASSEMBLY__
#include <asm/io.h>