| commit | 653f7c44677cd13bb106673bb7c46542e217fa13 | [log] [tgz] |
|---|---|---|
| author | Ley Foon Tan <ley.foon.tan@intel.com> | Mon May 04 18:41:55 2020 +0800 |
| committer | Tom Rini <trini@konsulko.com> | Wed May 06 15:12:48 2020 -0400 |
| tree | 9acf4fc82e747b1788bec31a07e6568e734a2f79 | |
| parent | 15c160301cf4761d45e09808f9d818525425901b [diff] |
cache: l2x0: Fix missing write to Auxiliary Control Register
In commit f62782fb2999 ("cache: l2x0: Fix write to incorrect shared-override
bit") we removed writel to regs->pl310_aux_ctrl by accident. This
commit restores it back.
Fixes: f62782fb2999 ("cache: l2x0: Fix write to incorrect shared-override bit")
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>