diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index c9f9e83..586ccbf 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -16,6 +16,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/grf_rk3288.h>
+#include <asm/arch/grf_rk3368.h>
 #include <asm/arch/grf_rk3399.h>
 #include <dm/pinctrl.h>
 #include <dt-bindings/clock/rk3288-cru.h>
@@ -83,6 +84,38 @@
 	return 0;
 }
 
+static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+{
+	struct rk3368_grf *grf;
+	int clk;
+	enum {
+		RK3368_GMAC_CLK_SEL_2_5M = 2 << 4,
+		RK3368_GMAC_CLK_SEL_25M = 3 << 4,
+		RK3368_GMAC_CLK_SEL_125M = 0 << 4,
+		RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4),
+	};
+
+	switch (priv->phydev->speed) {
+	case 10:
+		clk = RK3368_GMAC_CLK_SEL_2_5M;
+		break;
+	case 100:
+		clk = RK3368_GMAC_CLK_SEL_25M;
+		break;
+	case 1000:
+		clk = RK3368_GMAC_CLK_SEL_125M;
+		break;
+	default:
+		debug("Unknown phy speed: %d\n", priv->phydev->speed);
+		return -EINVAL;
+	}
+
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk);
+
+	return 0;
+}
+
 static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
 {
 	struct rk3399_grf_regs *grf;
@@ -129,6 +162,44 @@
 		     pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
 }
 
+static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+{
+	struct rk3368_grf *grf;
+	enum {
+		RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9,
+		RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9),
+		RK3368_RMII_MODE_MASK  = BIT(6),
+		RK3368_RMII_MODE       = BIT(6),
+	};
+	enum {
+		RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15),
+		RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+		RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15),
+		RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7),
+		RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+		RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7),
+		RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8,
+		RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8),
+		RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0,
+		RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
+	};
+
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	rk_clrsetreg(&grf->soc_con15,
+		     RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK,
+		     RK3368_GMAC_PHY_INTF_SEL_RGMII);
+
+	rk_clrsetreg(&grf->soc_con16,
+		     RK3368_RXCLK_DLY_ENA_GMAC_MASK |
+		     RK3368_TXCLK_DLY_ENA_GMAC_MASK |
+		     RK3368_CLK_RX_DL_CFG_GMAC_MASK |
+		     RK3368_CLK_TX_DL_CFG_GMAC_MASK,
+		     RK3368_RXCLK_DLY_ENA_GMAC_ENABLE |
+		     RK3368_TXCLK_DLY_ENA_GMAC_ENABLE |
+		     pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT |
+		     pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT);
+}
+
 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 {
 	struct rk3399_grf_regs *grf;
@@ -208,6 +279,11 @@
 	.set_to_rgmii = rk3288_gmac_set_to_rgmii,
 };
 
+const struct rk_gmac_ops rk3368_gmac_ops = {
+	.fix_mac_speed = rk3368_gmac_fix_mac_speed,
+	.set_to_rgmii = rk3368_gmac_set_to_rgmii,
+};
+
 const struct rk_gmac_ops rk3399_gmac_ops = {
 	.fix_mac_speed = rk3399_gmac_fix_mac_speed,
 	.set_to_rgmii = rk3399_gmac_set_to_rgmii,
@@ -216,6 +292,8 @@
 static const struct udevice_id rockchip_gmac_ids[] = {
 	{ .compatible = "rockchip,rk3288-gmac",
 	  .data = (ulong)&rk3288_gmac_ops },
+	{ .compatible = "rockchip,rk3368-gmac",
+	  .data = (ulong)&rk3368_gmac_ops },
 	{ .compatible = "rockchip,rk3399-gmac",
 	  .data = (ulong)&rk3399_gmac_ops },
 	{ }