MPC85xx: Add MPC8569MDS board support
This patch adds MPC8569MDS board support. The UART, QE UEC1 and UEC2, BRD
EEPROM on I2C2 bus, PCI express and DDR3 SPD are supported in this patch.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Hillel Avni <Hillel.Avni@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
diff --git a/board/freescale/mpc8569mds/Makefile b/board/freescale/mpc8569mds/Makefile
new file mode 100644
index 0000000..23805ea
--- /dev/null
+++ b/board/freescale/mpc8569mds/Makefile
@@ -0,0 +1,55 @@
+#
+# Copyright 2004-2009 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y += $(BOARD).o
+COBJS-y += bcsr.o
+COBJS-y += ddr.o
+COBJS-y += law.o
+COBJS-y += tlb.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mpc8569mds/bcsr.c b/board/freescale/mpc8569mds/bcsr.c
new file mode 100644
index 0000000..5adffc2
--- /dev/null
+++ b/board/freescale/mpc8569mds/bcsr.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#include "bcsr.h"
+
+void enable_8569mds_flash_write()
+{
+ setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 11), BCSR17_FLASH_nWP);
+}
+
+void disable_8569mds_flash_write()
+{
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
+}
+
+void enable_8569mds_qe_mdio()
+{
+ setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
+ BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
+ setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
+ BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
+}
+
+void disable_8569mds_brd_eeprom_write_protect()
+{
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), BCSR7_BRD_WRT_PROTECT);
+}
diff --git a/board/freescale/mpc8569mds/bcsr.h b/board/freescale/mpc8569mds/bcsr.h
new file mode 100644
index 0000000..8efe9bd
--- /dev/null
+++ b/board/freescale/mpc8569mds/bcsr.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __BCSR_H_
+#define __BCSR_H_
+
+#include <common.h>
+
+/* BCSR Bit definitions*/
+/****************************************/
+/* BCSR defines */
+/****************************************/
+#define BCSR6_UPC1_EN 0x80
+#define BCSR6_UPC1_POS_EN 0x40
+#define BCSR6_UPC1_ADDR_EN 0x20
+#define BCSR6_UPC1_DEV2 0x10
+#define BCSR6_SD_ENABLE 0x04
+#define BCSR6_TDM2G_EN 0x02
+#define BCSR6_UCC7_RMII_EN 0x01
+
+#define BCSR7_UCC1_GETH_EN 0x80
+#define BCSR7_UCC1_RGMII_EN 0x40
+#define BCSR7_UCC1_RTBI_EN 0x20
+#define BCSR7_GETHRST_MRVL 0x04
+#define BCSR7_BRD_WRT_PROTECT 0x02
+
+#define BCSR8_UCC2_GETH_EN 0x80
+#define BCSR8_UCC2_RGMII_EN 0x40
+#define BCSR8_UCC2_RTBI_EN 0x20
+#define BCSR8_UEM_MARVEL_RESET 0x02
+
+#define BCSR9_UCC3_GETH_EN 0x80
+#define BCSR9_UCC3_RGMII_EN 0x40
+#define BCSR9_UCC3_RTBI_EN 0x20
+#define BCSR9_UCC3_RMII_EN 0x10
+#define BCSR9_UCC3_UEM_MICREL 0x01
+
+#define BCSR10_UCC4_GETH_EN 0x80
+#define BCSR10_UCC4_RGMII_EN 0x40
+#define BCSR10_UCC4_RTBI_EN 0x20
+
+#define BCSR11_LED0 0x40
+#define BCSR11_LED1 0x20
+#define BCSR11_LED2 0x10
+
+#define BCSR12_UCC6_RMII_EN 0x20
+#define BCSR12_UCC8_RMII_EN 0x20
+
+#define BCSR15_SMII6_DIS 0x08
+#define BCSR15_SMII8_DIS 0x04
+
+#define BCSR16_UPC1_DEV2 0x02
+
+#define BCSR17_FLASH_nWP 0x01
+
+/*BCSR Utils functions*/
+
+void enable_8569mds_flash_write(void);
+void disable_8569mds_flash_write(void);
+void enable_8569mds_qe_mdio(void);
+void disable_8569mds_brd_eeprom_write_protect(void);
+
+#endif /* __BCSR_H_ */
diff --git a/board/freescale/mpc8569mds/config.mk b/board/freescale/mpc8569mds/config.mk
new file mode 100644
index 0000000..36b344e
--- /dev/null
+++ b/board/freescale/mpc8569mds/config.mk
@@ -0,0 +1,30 @@
+#
+# Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8569mds board
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8569=1
diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c
new file mode 100644
index 0000000..4b4533e
--- /dev/null
+++ b/board/freescale/mpc8569mds/ddr.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void
+get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+ i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t));
+}
+
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+ return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
+ unsigned int ctrl_num)
+{
+ unsigned int i;
+ unsigned int i2c_address = 0;
+
+ for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+ if (ctrl_num == 0 && i == 0)
+ i2c_address = SPD_EEPROM_ADDRESS1;
+ if (ctrl_num == 0 && i == 1)
+ i2c_address = SPD_EEPROM_ADDRESS2;
+ get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+ }
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ /*
+ * Factors to consider for clock adjust:
+ * - number of chips on bus
+ * - position of slot
+ * - DDR1 vs. DDR2?
+ * - ???
+ *
+ * This needs to be determined on a board-by-board basis.
+ * 0110 3/4 cycle late
+ * 0111 7/8 cycle late
+ */
+ popts->clk_adjust = 6;
+
+ /*
+ * Factors to consider for CPO:
+ * - frequency
+ * - ddr1 vs. ddr2
+ */
+ popts->cpo_override = 0xff;
+
+ /*
+ * Factors to consider for write data delay:
+ * - number of DIMMs
+ *
+ * 1 = 1/4 clock delay
+ * 2 = 1/2 clock delay
+ * 3 = 3/4 clock delay
+ * 4 = 1 clock delay
+ * 5 = 5/4 clock delay
+ * 6 = 3/2 clock delay
+ */
+ popts->write_data_delay = 2;
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+}
diff --git a/board/freescale/mpc8569mds/law.c b/board/freescale/mpc8569mds/law.c
new file mode 100644
index 0000000..e7381aa
--- /dev/null
+++ b/board/freescale/mpc8569mds/law.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ *0) 0x0000_0000 0x7fff_ffff DDR 2G
+ *1) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB
+ *-) 0xe000_0000 0xe00f_ffff CCSR 1M
+ *2) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M
+ *3) 0xc000_0000 0xdfff_ffff SRIO 512MB
+ *4.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB
+ *4.b) 0xf800_0000 0xf800_7fff BCSR 32KB
+ *4.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB
+ *4.d) 0xf801_0000 0xf801_7fff PIB (CS5) 32KB
+ *4.e) 0xfe00_0000 0xffff_ffff Flash 32MB
+ *
+ *Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ */
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SPD_EEPROM
+ SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_1G, LAW_TRGT_IF_DDR),
+#endif
+ SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c
new file mode 100644
index 0000000..53fef43
--- /dev/null
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -0,0 +1,329 @@
+/*
+ * Copyright 2009 Freescale Semiconductor.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/immap_fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/io.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include <ioports.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#include "bcsr.h"
+
+phys_size_t fixed_sdram(void);
+
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+ /* QE_MUX_MDC */
+ {2, 31, 1, 0, 1}, /* QE_MUX_MDC */
+
+ /* QE_MUX_MDIO */
+ {2, 30, 3, 0, 2}, /* QE_MUX_MDIO */
+
+ /* UCC_1_RGMII */
+ {2, 11, 2, 0, 1}, /* CLK12 */
+ {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
+ {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
+ {0, 2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2 */
+ {0, 3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
+ {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
+ {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
+ {0, 8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
+ {0, 9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
+ {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
+ {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
+ {2, 8, 2, 0, 1}, /* ENET1_GRXCLK */
+ {2, 20, 1, 0, 2}, /* ENET1_GTXCLK */
+
+ /* UCC_2_RGMII */
+ {2, 16, 2, 0, 3}, /* CLK17 */
+ {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
+ {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
+ {0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2 */
+ {0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3 */
+ {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
+ {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
+ {0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2 */
+ {0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3 */
+ {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
+ {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
+ {2, 3, 2, 0, 1}, /* ENET2_GRXCLK */
+ {2, 2, 1, 0, 2}, /* ENET2_GTXCLK */
+
+ {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
+};
+
+void local_bus_init(void);
+
+int board_early_init_f (void)
+{
+ /*
+ * Initialize local bus.
+ */
+ local_bus_init ();
+
+ enable_8569mds_flash_write();
+
+#ifdef CONFIG_QE
+ enable_8569mds_qe_mdio();
+#endif
+
+#if CONFIG_SYS_I2C2_OFFSET
+ /* Enable I2C2 signals instead of SD signals */
+ volatile struct ccsr_gur *gur;
+ gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000);
+ gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK;
+ gur->plppar1 |= PLPPAR1_I2C2_VAL;
+ gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK;
+ gur->plpdir1 |= PLPDIR1_I2C2_VAL;
+
+ disable_8569mds_brd_eeprom_write_protect();
+#endif
+
+ return 0;
+}
+
+int checkboard (void)
+{
+ printf ("Board: 8569 MDS\n");
+
+ return 0;
+}
+
+phys_size_t
+initdram(int board_type)
+{
+ long dram_size = 0;
+
+ puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+ /*
+ * Work around to stabilize DDR DLL MSYNC_IN.
+ * Errata DDR9 seems to have been fixed.
+ * This is now the workaround for Errata DDR11:
+ * Override DLL = 1, Course Adj = 1, Tap Select = 0
+ */
+ volatile ccsr_gur_t *gur =
+ (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ out_be32(&gur->ddrdllcr, 0x81000000);
+ udelay(200);
+#endif
+
+#ifdef CONFIG_SPD_EEPROM
+ dram_size = fsl_ddr_sdram();
+#else
+ dram_size = fixed_sdram();
+#endif
+
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+ puts(" DDR: ");
+ return dram_size;
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+phys_size_t fixed_sdram(void)
+{
+ volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+ uint d_init;
+
+ out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
+ out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
+ out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+ out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+ out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+ out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+ out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
+ out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
+ out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE);
+ out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2);
+ out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL);
+ out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
+ out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
+ out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
+ out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
+ out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
+ out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
+ out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
+#if defined (CONFIG_DDR_ECC)
+ out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN);
+ out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS);
+ out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE);
+#endif
+ udelay(500);
+
+ out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
+#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ d_init = 1;
+ debug("DDR - 1st controller: memory initializing\n");
+ /*
+ * Poll until memory is initialized.
+ * 512 Meg at 400 might hit this 200 times or so.
+ */
+ while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
+ udelay(1000);
+ }
+ debug("DDR: memory initialized\n\n");
+ udelay(500);
+#endif
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+}
+#endif
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+
+ uint clkdiv;
+ uint lbc_hz;
+ sys_info_t sysinfo;
+
+ get_sys_info(&sysinfo);
+ clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
+ lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+ out_be32(&gur->lbiuiplldcr1, 0x00078080);
+ if (clkdiv == 16)
+ out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
+ else if (clkdiv == 8)
+ out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
+ else if (clkdiv == 4)
+ out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
+
+ out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000);
+}
+
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif /* CONFIG_PCIE1 */
+
+extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
+extern void fsl_pci_init(struct pci_controller *hose);
+
+int first_free_busno = 0;
+
+#ifdef CONFIG_PCI
+void
+pci_init_board(void)
+{
+ volatile ccsr_gur_t *gur;
+ uint io_sel;
+ uint host_agent;
+
+ gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+ host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+
+#ifdef CONFIG_PCIE1
+{
+ volatile ccsr_fsl_pci_t *pci;
+ struct pci_controller *hose;
+ int pcie_ep;
+ struct pci_region *r;
+ int pcie_configured;
+
+ pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
+ hose = &pcie1_hose;
+ pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
+ r = hose->regions;
+ pcie_configured = io_sel >= 1;
+
+ if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
+ printf ("\n PCIE connected to slot as %s (base address %x)",
+ pcie_ep ? "End Point" : "Root Complex",
+ (uint)pci);
+
+ if (pci->pme_msg_det) {
+ pci->pme_msg_det = 0xffffffff;
+ debug (" with errors. Clearing. Now 0x%08x",
+ pci->pme_msg_det);
+ }
+ printf ("\n");
+
+ /* inbound */
+ r += fsl_pci_setup_inbound_windows(r);
+
+ /* outbound memory */
+ pci_set_region(r++,
+ CONFIG_SYS_PCIE1_MEM_BUS,
+ CONFIG_SYS_PCIE1_MEM_PHYS,
+ CONFIG_SYS_PCIE1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(r++,
+ CONFIG_SYS_PCIE1_IO_BUS,
+ CONFIG_SYS_PCIE1_IO_PHYS,
+ CONFIG_SYS_PCIE1_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = r - hose->regions;
+
+ hose->first_busno=first_free_busno;
+ pci_setup_indirect(hose, (int) &pci->cfg_addr,
+ (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+ printf ("PCIE on bus %02x - %02x\n",
+ hose->first_busno,hose->last_busno);
+
+ first_free_busno=hose->last_busno+1;
+
+ } else {
+ printf (" PCIE: disabled\n");
+ }
+}
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+#endif
+}
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+ struct pci_controller *hose);
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_PCIE1
+ ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
+#endif
+}
+#endif
diff --git a/board/freescale/mpc8569mds/tlb.c b/board/freescale/mpc8569mds/tlb.c
new file mode 100644
index 0000000..d3b251e
--- /dev/null
+++ b/board/freescale/mpc8569mds/tlb.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 Initializations */
+ /*
+ * TLBe 0: 16M Non-cacheable, guarded
+ * 0xff000000 16M FLASH (upper half)
+ * Out of reset this entry is only 4K.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000,
+ CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_16M, 1),
+
+ /*
+ * TLBe 1: 16M Non-cacheable, guarded
+ * 0xfe000000 16M FLASH (lower half)
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /*
+ * TLBe 2: 256M Non-cacheable, guarded
+ * 0xa00000000 256M PCIe MEM (lower half)
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLBe 3: 256M Non-cacheable, guarded
+ * 0xb00000000 256M PCIe MEM (higher half)
+ */
+ SET_TLB_ENTRY(1, (CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000),
+ (CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000),
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLBe 4: 64M Non-cacheable, guarded
+ * 0xe000_0000 1M CCSRBAR
+ * 0xe280_0000 8M PCIe IO
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_64M, 1),
+
+ /*
+ * TLBe 5: 256K Non-cacheable, guarded
+ * 0xf8000000 32K BCSR
+ * 0xf8008000 32K PIB (CS4)
+ * 0xf8010000 32K PIB (CS5)
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256K, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8569mds/u-boot.lds b/board/freescale/mpc8569mds/u-boot.lds
new file mode 100644
index 0000000..0b2ea75
--- /dev/null
+++ b/board/freescale/mpc8569mds/u-boot.lds
@@ -0,0 +1,143 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+PHDRS
+{
+ text PT_LOAD;
+ bss PT_LOAD;
+}
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ } :text
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.eh_frame)
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ } :text
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ .bootpg ADDR(.text) + 0x7f000 :
+ {
+ cpu/mpc85xx/start.o (.bootpg)
+ } :text = 0xffff
+
+ .resetvec ADDR(.text) + 0x7fffc :
+ {
+ *(.resetvec)
+ } :text = 0xffff
+
+ . = ADDR(.text) + 0x80000;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ } :bss
+
+ . = ALIGN(4);
+ _end = . ;
+ PROVIDE (end = .);
+}