| commit | 70ed80af46e58a25d472362fe5552e1e49eaf25b | [log] [tgz] |
|---|---|---|
| author | Marek Vasut <marex@denx.de> | Mon Apr 04 21:16:18 2016 +0200 |
| committer | Marek Vasut <marex@denx.de> | Wed Apr 20 11:28:45 2016 +0200 |
| tree | a6eec9f88741935b64ae39157a42f17aab48878e | |
| parent | f3f777cdf00433866b1178e23a9a99e2eaf7d89e [diff] |
ddr: altera: Zero DM IN delay in scc_mgr_zero_group() This one last set of delay configuration registers was not properly zeroed out originally, fix it and zero them out. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>