board: atmel: clean up peripheral clock code
Due to introducing the new peripheral clock handle functions,
use these functions to reduce duplicated code.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
[Rebased on current master, fixup for at91rm9200ek]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
diff --git a/board/mini-box/picosam9g45/picosam9g45.c b/board/mini-box/picosam9g45/picosam9g45.c
index 193f14d..32ba9c6 100644
--- a/board/mini-box/picosam9g45/picosam9g45.c
+++ b/board/mini-box/picosam9g45/picosam9g45.c
@@ -17,7 +17,6 @@
#include <asm/arch/at91sam9g45_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
#include <lcd.h>
@@ -80,15 +79,13 @@
void mem_init(void)
{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
struct atmel_mpddrc_config ddr2;
unsigned long csa;
ddr2_conf(&ddr2);
- /* enable DDR2 clock */
- writel(AT91_PMC_DDR, &pmc->scer);
+ at91_system_clk_enable(AT91_PMC_DDR);
/* Chip select 1 is for DDR2/SDRAM */
csa = readl(&mat->ebicsa);
@@ -105,9 +102,7 @@
#ifdef CONFIG_CMD_USB
static void picosam9g45_usb_hw_init(void)
{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
+ at91_periph_clk_enable(ATMEL_ID_PIODE);
at91_set_gpio_output(AT91_PIN_PD1, 0);
at91_set_gpio_output(AT91_PIN_PD3, 0);
@@ -117,11 +112,9 @@
#ifdef CONFIG_MACB
static void picosam9g45_macb_hw_init(void)
{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
- /* Enable clock */
- writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
+ at91_periph_clk_enable(ATMEL_ID_EMAC);
/*
* Disable pull-up on:
@@ -181,8 +174,6 @@
static void picosam9g45_lcd_hw_init(void)
{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
@@ -214,7 +205,7 @@
at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
- writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
+ at91_periph_clk_enable(ATMEL_ID_LCDC);
gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
}