mpc83xx: serdes: add forgotten shifts for rfcks
The rfcks should be shifted by 28 bits left. We didn't notice the bug
because we were using only 100MHz clocks (for which rfcks == 0).
Though, for SGMII we'll need 125MHz clocks.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
diff --git a/cpu/mpc83xx/serdes.c b/cpu/mpc83xx/serdes.c
index 630b111..3936796 100644
--- a/cpu/mpc83xx/serdes.c
+++ b/cpu/mpc83xx/serdes.c
@@ -42,7 +42,7 @@
#define FSL_SRDSRSTCTL_RST 0x80000000
#define FSL_SRDSRSTCTL_SATA_RESET 0xf
-void fsl_setup_serdes(u32 offset, char proto, char rfcks, char vdd)
+void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd)
{
void *regs = (void *)CONFIG_SYS_IMMR + offset;
u32 tmp;